Abstract: A method for electrostatic discharge (ESD) protection of a chip is disclosed. The chip includes a driver, a first tri-state buffer, and a second tri-state buffer, wherein an output of the driver is coupled to a pad, an output of the first tri-state buffer is coupled to a first input of the driver, and an output of the second tri-state buffer is coupled to a second input of the driver. The method includes, during a normal mode, driving the first input of the driver with a first data signal using the first tri-state buffer and driving the second input of the driver with a second data signal using the second tri-state buffer. The method also includes detecting an ESD event on the pad, and, in response to detecting the ESD event, putting each of the first tri-state buffer and the second tri-state buffer in a high impedance output state.

Abstract: An equalizing transmitter coupled to a communication channel includes a plurality of driver segments, at least one equalizer segment, a delay element and a logic circuit. Each driver segment in the plurality of driver segments includes a pullup transistor that is configured to couple the communication channel to a first voltage rail when an input signal is in a first signaling state. The at least one equalizer segment includes a pullup transistor configured to couple the communication channel to the first voltage rail when turned on. The delay element is configured to provide a precursor signal that is a delayed version of the input signal. The logic circuit is responsive to the precursor signal and provides an enabling signal that enables the at least one equalizer segment to be turned on when the precursor signal is in a second signaling state.

Abstract: A method for operating a memory interface circuit includes generating an internal data strobe signal based on a first data strobe signal and a second data strobe signal using a first receiver, generating a qualifier signal based on the second data strobe signal and a reference voltage using a second receiver, delaying a rise time and a fall time of the qualifier signal using a delay adjuster, generating a gate control signal based on the internal data strobe signal and the qualifier signal after the delay adjuster, and gating a portion of the internal data strobe signal based on the gate control signal to provide a read clock signal.

Abstract: Various aspects of the present disclosure generally relate to memory devices. In some aspects, a device may generate a clock signal for a memory interface. The device may apply a clock leveling to one or more initial clock pulses associated with the clock signal. The device may stop the clock leveling for one or more remaining clock pulses associated with the clock signal. Numerous other aspects are described.

Abstract: A driver circuit includes a flipflop and a first plurality of series-coupled delay elements. The flipflop may be configured to encode a sequence of codewords in a multibit signal. The first plurality of series-coupled delay elements may be configured to propagate the multibit signal to a tuning circuit in the driver circuit during voltage ramping of a power supply used by the driver circuit. Each codeword in the sequence of codewords may be used to configure the tuning circuit during the voltage ramping of the power supply. The sequence of codewords may be configured to incrementally change impedance of the driver during the voltage ramping of the power supply.

Abstract: An amplifier includes first and second input transistors, a first current mirror, a second current mirror, and a third current mirror. An input terminal of the first current mirror is coupled to a drain of the first input transistor, an input terminal of the second current mirror is coupled to a drain of the second input transistor, and an input terminal of the third current mirror is coupled to an output terminal of the first current mirror. An output terminal of the first current mirror and an output terminal of the third current mirror are coupled to an output of the amplifier. The amplifier also includes third and fourth input transistors, wherein a drain of the third input transistor is coupled to the input terminal of the third current mirror, and a drain of the fourth input transistor is coupled to the output of the amplifier.

Abstract: An equalizing transmitter coupled to a communication channel includes a plurality of driver segments, at least one equalizer segment, a delay element and a logic circuit. Each driver segment in the plurality of driver segments includes a pullup transistor that is configured to couple the communication channel to a first voltage rail when an input signal is in a first signaling state. The at least one equalizer segment includes a pullup transistor configured to couple the communication channel to the first voltage rail when turned on. The delay element is configured to provide a precursor signal that is a delayed version of the input signal. The logic circuit is responsive to the precursor signal and provides an enabling signal that enables the at least one equalizer segment to be turned on when the precursor signal is in a second signaling state.

Abstract: A system includes a driver including a pull-up p-type field effect transistor (PFET). The system also includes a negative boost circuit. The negative boost circuit includes a first drive circuit configured to receive a first supply voltage, a second drive circuit configured to receive a second supply voltage different from the first supply voltage, a switch coupled between an output of the second drive circuit and a gate of the pull-up PFET, and a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the gate of the pull-up PFET and the second terminal is coupled to an output of the first drive circuit. The system also includes a pre-drive circuit configured to drive an input of the first drive circuit and an input of the second drive circuit based on an input signal.

Abstract: A calibration circuit has a delay loop, a counter and a latch. The delay loop that includes a delay circuit. The counter is clocked by edges in a clock signal generated by the delay loop when an enable signal is in a first signaling state. The latch is configured to capture a multibit output of the counter when the enable signal transitions to a second signaling state. A number of unit delay elements in the delay circuit are enabled based on the multibit output of the counter. In one example, the number of enabled unit delay elements is based on a difference between the multibit output of the counter and a multibit value expected to be generated when the delay circuit is operating nominally.

Abstract: A calibration circuit has a delay loop, a counter and a latch. The delay loop that includes a delay circuit. The counter is clocked by edges in a clock signal generated by the delay loop when an enable signal is in a first signaling state. The latch is configured to capture a multibit output of the counter when the enable signal transitions to a second signaling state. A number of unit delay elements in the delay circuit are enabled based on the multibit output of the counter. In one example, the number of enabled unit delay elements is based on a difference between the multibit output of the counter and a multibit value expected to be generated when the delay circuit is operating nominally.

Abstract: An apparatus has a first spiral coil on a first layer, a second spiral coil adjacent to the first spiral coil on the first layer, a third spiral coil on a second layer that is parallel to the first layer, and a fourth spiral coil adjacent to the third spiral coil on the second layer. The first spiral coil spirals inward in a first direction. The second spiral coil spirals inward in a second direction different from the first direction. The third spiral coil is arranged adjacent the first spiral coil. The fourth spiral coil is arranged adjacent the second spiral coil.

Abstract: A method for equalizing a data signal includes providing a data signal to a pair of input transistors that provides an output signal, contributing to the output signal, a first current or voltage that has a magnitude determined by a first weighted feedback signal using a first decision-feedback circuit that includes a first pullup circuit coupled to a drain of a first input transistor, and a first pulldown circuit coupled to the drain of the first input transistor, and contributing to the output signal, a second current or voltage that has a magnitude determined by a second weighted feedback signal using a second decision-feedback circuit that includes a second pullup circuit coupled between a drain of a second input transistor and the first voltage rail, and a second pulldown circuit coupled between the drain of the second input transistor and a second voltage rail.

Abstract: A method for operating a memory interface circuit includes generating an internal data strobe signal based on a first data strobe signal and a second data strobe signal using a first receiver, generating a qualifier signal based on the second data strobe signal and a reference voltage using a second receiver, delaying a rise time and a fall time of the qualifier signal using a delay adjuster, generating a gate control signal based on the internal data strobe signal and the qualifier signal after the delay adjuster, and gating a portion of the internal data strobe signal based on the gate control signal to provide a read clock signal.

Abstract: A system includes a driver including a pull-up p-type field effect transistor (PFET). The system also includes a negative boost circuit. The negative boost circuit includes a first drive circuit configured to receive a first supply voltage, a second drive circuit configured to receive a second supply voltage different from the first supply voltage, a switch coupled between an output of the second drive circuit and a gate of the pull-up PFET, and a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the gate of the pull-up PFET and the second terminal is coupled to an output of the first drive circuit. The system also includes a pre-drive circuit configured to drive an input of the first drive circuit and an input of the second drive circuit based on an input signal.

Abstract: A driver circuit includes a flipflop and a first plurality of series-coupled delay elements. The flipflop may be configured to encode a sequence of codewords in a multibit signal. The first plurality of series-coupled delay elements may be configured to propagate the multibit signal to a tuning circuit in the driver circuit during voltage ramping of a power supply used by the driver circuit. Each codeword in the sequence of codewords may be used to configure the tuning circuit during the voltage ramping of the power supply. The sequence of codewords may be configured to incrementally change impedance of the driver during the voltage ramping of the power supply.

Abstract: An integrated circuit (IC) including a first transceiver interface circuit extending longitudinally in a first direction substantially perpendicular to a second direction parallel to edge of the IC, wherein the first transceiver interface circuit comprises a first T-coil; and a second transceiver interface circuit extending longitudinally in the first direction, wherein the second transceiver interface circuit is staggered from the first transceiver interface circuit along the second direction, wherein the second transceiver interface circuit includes a second T-coil, and wherein the second T-coil is offset from the first T-coil along the first direction.

Abstract: A method for equalizing a data signal includes providing a data signal to a pair of input transistors that provides an output signal, contributing to the output signal, a first current or voltage that has a magnitude determined by a first weighted feedback signal using a first decision-feedback circuit that includes a first pullup circuit coupled to a drain of a first input transistor, and a first pulldown circuit coupled to the drain of the first input transistor, and contributing to the output signal, a second current or voltage that has a magnitude determined by a second weighted feedback signal using a second decision-feedback circuit that includes a second pullup circuit coupled between a drain of a second input transistor and the first voltage rail, and a second pulldown circuit coupled between the drain of the second input transistor and a second voltage rail.

Abstract: An apparatus and method of generating an output transmit signal including generating a first portion of an output transmit signal based on an input transmit signal, wherein the first portion of the output transmit signal includes a first set of pulses each spanning a unit interval (UI); generating a second portion of the output transmit signal based on the input transmit signal, wherein the second portion of the output signal includes a second set of pulses each spanning a middle sub-interval of the UI; and combining the first portion with the second portion to generate the output transmit signal.

Abstract: A memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source, a second differential receiver configured to receive a differential data strobe signal in a pair of complementary signals, a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the pair of complementary signals, a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

Abstract: An integrated circuit (IC) including a first transceiver interface circuit extending longitudinally in a first direction substantially perpendicular to a second direction parallel to edge of the IC, wherein the first transceiver interface circuit comprises a first T-coil; and a second transceiver interface circuit extending longitudinally in the first direction, wherein the second transceiver interface circuit is staggered from the first transceiver interface circuit along the second direction, wherein the second transceiver interface circuit includes a second T-coil, and wherein the second T-coil is offset from the first T-coil along the first direction.