Patents by Inventor Patrick J. Eichenseer

Patrick J. Eichenseer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7155694
    Abstract: In accordance with a method for generating a trial placement plan for an IC having two or more identical modules, a floor plan reserves a separate area of identical size and shape for each of the identical modules, one of which is designated a “master module” and the others designated “clone modules”. A placement and routing (P&R) tool initially places all of the cell instances of the clone modules at the center of their reserved areas. The P&R tool then employs a conventional placement algorithm to iteratively adjust positions of cell instances of all other modules, including the master module within their reserved areas in a manner that tries to minimize net lengths. The P&R tool copies the placement within the master module area into the clone module areas either after every N>0 iterations of the placement algorithm and/or after the placement algorithm has completed placement for the master module area.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: December 26, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Patrick J. Eichenseer, Hsi-Chuan Chen, Dennis Huang