Patents by Inventor Patrick J. McGuire

Patrick J. McGuire has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of providing a family of related integrated circuits of different sizes
    Patent number: 7498192
    Abstract: Methods of manufacturing a family of packaged integrated circuits (ICs) having at least two different logic capacities. A first IC die includes two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A first set of the first IC dies are packaged such that both portions of the dies are operational. A second set of the first IC dies are packaged such that only the first portion of each die is operational. Once the first and second sets are packaged and the second set of ICs has been evaluated, a decision is made whether or not to manufacture a second IC die that includes the first portion of the first die, while excluding the second portion.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: March 3, 2009
    Assignee: Xilinx, Inc.
    Inventors: F. Erich Goetting, Trevor J. Bauer, Patrick J. McGuire, Bruce E. Talley, Paul Ying-Fung Wu, Steven P. Young
  • Yield-enhancing methods of providing a family of scaled integrated circuits
    Patent number: 7491576
    Abstract: An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: February 17, 2009
    Assignee: Xilinx, Inc.
    Inventors: Steven P. Young, Trevor J. Bauer, F. Erich Goetting, P. Hugo Lamarche, Patrick J. McGuire, Kwansuhk Oh, Raymond C. Pang, Bruce E. Talley, Paul Ying-Fung Wu
  • Multi-product die configurable as two or more programmable integrated circuits of different logic capacities
    Patent number: 7345507
    Abstract: A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: March 18, 2008
    Assignee: Xilinx, Inc.
    Inventors: Steven P. Young, Trevor J. Bauer, F. Erich Goetting, P. Hugo Lamarche, Patrick J. McGuire, Kwansuhk Oh, Raymond C. Pang, Bruce E. Talley, Paul Ying-Fung Wu