Abstract: A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many applications. In a preferred embodiment for an L2 cache, the system transmits congruence class data in the first half and can start to access the L2 cache directory with the congruence class data.

Abstract: Disclosed is a method and apparatus for arbitration between multiple pipelines over shared resources for an SMP computer system. The computer includes logic to defer arbitration until later in the pipeline to help reduce latency to each pipeline. Also, introduced is the concept of retry tags for better priority to avoid lock-out. The system also includes round-robin tokens to manage rejected requests to allow better fairness on conflicts. While the processing logic employed specifically applies to cross-interrogation, the logic can be extended to other common resources. The illustrated SMP computer system also has self-correcting logic to maintain good round-robin tokens.

Abstract: A double data rate elastic interface in which programmable latch stages provide an elastic delay, preferably on the driving side of the elastic interface. However, the invention is not limited to the driver side/chip, it can be implemented in the receiver side/chip as well. However, since the receiver side of an elastic interface already has complicated logic, the invention will be usually implemented on the driving side. The programmable latch stages on the driving chip side of the interface, can often operate at the local clock frequency (the same frequency as the elastic interface bus clock frequency), which in turn is half of the double data rate at which the receiving latch stages operate, thereby decreasing the logic and storage resources in the interface receivers. The programmable latch stages can also be used in the case that the local clock frequency is twice the elastic interface bus clock frequency.

Abstract: A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.

Abstract: A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.

Abstract: Systems, methods and computer program products for providing a nested two-bit symbol bus error correcting code. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code. A symbol correcting code H-matrix is created by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes a symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.

Abstract: A system for processing errors in a processor comprising, a first register having a unique identifier operative to store a first error data, a processor operative to retrieve the first error data from the first register, associate the first error data with the unique identifier, and generate a first uniform error packet including the first error data and the unique identifier and a storage medium operative to store the first uniform error packet.

Abstract: A system for processing errors in a processor comprising, an error counter, a pass counter, and a processing portion operative to determine whether a first error is active, increment an error counter responsive to determining that the first error is active, increment the pass counter responsive to determining that all errors have been checked, and clear the error counter responsive to determining that the pass counter is greater than or equal to a pass count threshold value.

Abstract: Methods and means of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.

Abstract: An apparatus and method for protecting a computer system from array reliability failures uses Array Built-In Self-Test logic along with code and hardware to delete cache lines or sets that are defective, identify corresponding fuse repair values, proactively call home if spare fuses are not available, schedule soft fuse repairs for the next system restart, schedule line deletes at the next restart, store delete and fuse repairs in a table (tagged with electronic serial id, timestamp of delete or ABIST fail event, address, and type of failure) and proactively call home if there were any missed deletes that were not logged. Fuse information can also be more permanently stored into hardware electronic fuses and/or EPROMs. During a restart, previous repairs are able to be applied to the machine so that ABIST will run successfully and previous deletes to be maintained with checking to allow some ABIST failures which are protected by the line deletes to pass.

Abstract: A method and apparatus are disclosed for performing maintenance operations in a system using address, data, and controls which are transported through the system, allowing for parallel and serial operations to co-exist without the parallel operations being slowed down by the serial ones. It also provides for use of common shifters, engines, and protocols as well as efficient conversion of ECC to parity and parity to ECC as needed in the system. The invention also provides for error detection and isolation, both locally and in the reported status. The invention provides for large maintenance address and data spaces (typically 64 bits address and 64 bits data per address supported).

Abstract: A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

Abstract: A method of error correction code (ECC) debugging for a system comprising, receiving data having an ECC, determining whether a data error has occurred, generating a syndrome of an error result, decoding flipped data bits, processing the received data and the decoded flipped bits to correct the data, outputting corrected data having an ECC, receiving a trap update signal, and saving the decoded flipped data bits responsive to receiving the trap update signal.

Abstract: A computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic, a stability window delay counter, and a mux/register pair to allow for the holding of previous stable data during the transition. While the processing logic employed specifically applies to asynchronous logic, the logic can be extended to synchronous or untimed interfaces as well. Also disclosed is a programmable means to adjust the window delay.

Abstract: The present invention provides a new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

Abstract: A method and computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic, a stability window delay counter, and a mux/register pair to allow for the holding of previous stable data during the transition. While the processing logic employed specifically applies to asynchronous logic, the logic can be extended to synchronous or untimed interfaces as well. Also disclosed is a programmable means to adjust the window delay.

Abstract: An apparatus and method for allowing for dynamic wordline repair in a clock running system in addition to allowing for programmable fuse support of combined Array Built-In Self-Test (ABIST) and Logic Built-In Self-Test (LBIST) testing. The method makes use of programmable fuses which contain Level Sensitive Scan Design (LSSD) latches which also have a system port. The system port allows for simpler reading of the fuses as well as for the dynamic updates of the programmable fuses for wordline and other repairs.

Abstract: A method and computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic, a stability window delay counter, and a mux/register pair to allow for the holding of previous stable data during the transition. While the processing logic employed specifically applies to asynchronous logic, the logic can be extended to synchronous or untimed interfaces as well. Also disclosed is a programmable means to adjust the window delay.

Abstract: A method for deferred logging of machine data following an error or event in order to capture critical information for that error or event treats the data as persistent and it does not get logged until a disruption occurs to the system (e.g. system reset, restart, deactivation, or powered-down). This way, important debug data can be held in the hardware or software, without a need for complicated hardware and code for logging this debug data. Methods are also disclosed for setting a switch to indicate deferred logging is required, referencing the log data with the original event information, calling home with the debug data, resetting the deferred logging switch, setting the deferred logging switch manually, viewing whether the switch is already set, and supporting different kinds of switches.

Abstract: A method is disclosed for improving design criteria and importantly timing criteria following a metal-only engineering change. The method involves making initial logical changes involving new books (gate-level, filler-cell circuits, called ‘eco books’), running placement and routing with the new books, and timing the resulting logic. If there are timing violations, existing, non-filler books which are in close proximity are considered for swapping with the eco books. The book swaps are all done with wire connections only (i.e. the book placements are not affected). This way, critical paths and non-critical paths can be traded-off to achieve a faster design, even though books are not allowed to be moved. Some simple algorithms are discussed; however, there are many heuristic and analytic algorithms that can be applied in choosing swaps, based on the needs of the particular design.