Patents by Inventor Patrick J. Quirk
Patrick J. Quirk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12768183Abstract: The present disclosure provides for a modular design and build architecture, comprising: one or more integrated system module (ISMs) that are configured to be shipped and assembled on-site to construct an operational infrastructure for one or more application environments, wherein each of the ISMs comprises two or more different functional components that are integrated onto and/or supported by a common structural floor.Type: GrantFiled: February 9, 2024Date of Patent: October 20, 2026Assignee: Nautilus TRUE, LLCInventors: Gabe Andrews, Chase Abercrombie Ott, Robert C. Pfleging, Patrick J. Quirk
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Patent number: 12727124Abstract: Embodiments disclosed include a data center comprising a first reconfigurable utility module comprising interfaces for facilitating electrical power supply, data connectivity, and cooling media supply, and further comprising a plurality of interfaces through which components may be connected to said first reconfigurable utility module. Additionally, a plurality of server modules are connected to the reconfigurable utility module through the interfaces, each of said server modules comprising one or more racks of servers, each of said server modules receiving said power supply, said data connectivity, and said cooling media through an interface through which it is connected to said reconfigurable utility module.Type: GrantFiled: November 19, 2021Date of Patent: September 1, 2026Assignee: Nautilus TRUE, LLCInventors: Arnold Castillo Magcale, Patrick J. Quirk, Chase Abercrombie Ott, Robert C. Pfleging, Gabe Andrews
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Publication number: 20260082524Abstract: The present disclosure provides for a modular design and build architecture, comprising: one or more integrated system module (ISMs) that are configured to be shipped and assembled on-site to construct an operational infrastructure for one or more application environments, wherein each of the ISMs comprises two or more different functional components that are integrated onto and/or supported by a common structural floor.Type: ApplicationFiled: November 21, 2025Publication date: March 19, 2026Inventors: Gabe ANDREWS, Chase Abercrombie OTT, Robert C. PFLEGING, Patrick J. QUIRK, Arnold Castillo MAGCALE
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Publication number: 20250052054Abstract: The present disclosure provides for a modular design and build architecture, comprising: one or more integrated system module (ISMs) that are configured to be shipped and assembled on-site to construct an operational infrastructure for one or more application environments, wherein each of the ISMs comprises two or more different functional components that are integrated onto and/or supported by a common structural floor.Type: ApplicationFiled: September 13, 2024Publication date: February 13, 2025Inventors: Gabe ANDREWS, Chase Abercrombie OTT, Robert C. PFLEGING, Patrick J. QUIRK
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Publication number: 20240254788Abstract: The present disclosure provides for a modular design and build architecture, comprising: one or more integrated system module (ISMs) that are configured to be shipped and assembled on-site to construct an operational infrastructure for one or more application environments, wherein each of the ISMs comprises two or more different functional components that are integrated onto and/or supported by a common structural floor.Type: ApplicationFiled: February 9, 2024Publication date: August 1, 2024Inventors: Gabe ANDREWS, Chase Abercrombie OTT, Robert C. PFLEGING, Patrick J. QUIRK
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Patent number: 11946269Abstract: The present disclosure provides for a modular design and build architecture, comprising: one or more integrated system module (ISMs) that are configured to be shipped and assembled on-site to construct an operational infrastructure for one or more application environments, wherein each of the ISMs comprises two or more different functional components that are integrated onto and/or supported by a common structural floor.Type: GrantFiled: November 4, 2022Date of Patent: April 2, 2024Assignee: Nautilus TRUE, LLCInventors: Gabe Andrews, Chase Abercrombie Ott, Robert C. Pfleging, Patrick J. Quirk
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Publication number: 20230295940Abstract: The present disclosure provides for a modular design and build architecture, comprising: one or more integrated system module (ISMs) that are configured to be shipped and assembled on-site to construct an operational infrastructure for one or more application environments, wherein each of the ISMs comprises two or more different functional components that are integrated onto and/or supported by a common structural floor.Type: ApplicationFiled: November 4, 2022Publication date: September 21, 2023Inventors: Gabe ANDREWS, Chase Abercrombie OTT, Robert C. PFLEGING, Patrick J. QUIRK
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Patent number: 8132027Abstract: In one embodiment, a powered device (PD) (402) has a PHY module (410) and a media access controller (419) (MAC), the PD (402) adapted to connect to power sourcing equipment (PSE) via a cable, (408) where the PD (402) is adapted to communicate with and receive power from the PSE via the cable, in accordance with the Power-over-Ethernet (PoE) standard. The PD (402) extracts (413) from the cable (408) a DC signal used to power the PD without using a transformer. Capacitors (420) located in the signal paths between the MAC (419) and the cable (408) support electrical isolation of the MAC (419).Type: GrantFiled: June 16, 2006Date of Patent: March 6, 2012Assignee: Agere Systems Inc.Inventors: Matthew Blaha, Luis de La Torre, Alan L. Ellis, Gary D. Polhemhus, Patrick J. Quirk
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Patent number: 7843670Abstract: One embodiment monitors a line-side electrical current provided by a power sourcing equipment (PSE) port to a powered device (PD), the PSE port having a power-isolation transformer with a primary coil on an isolated side and a secondary coil on a line side. A switching signal having a switching period and a duty cycle is applied to the primary coil of the power-isolation transformer. A value is determined for an electrical current on the isolated side of the power-isolation transformer, conversion is performed between a line-side electrical current value Iout and a corresponding isolated-side peak-current value Ipeak, and the line-side electrical current is indirectly monitored based on the determined isolated-side current value.Type: GrantFiled: September 29, 2006Date of Patent: November 30, 2010Assignee: Agere Systems Inc.Inventors: Matthew Blaha, Luis de la Torre, Patrick J. Quirk, Fadi Saibi
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Publication number: 20100218003Abstract: In one embodiment, a powered device (PD) (402) has a PHY module (410) and a media access controller (419) (MAC), the PD (402) adapted to connect to power sourcing equipment (PSE) via a cable, (408) where the PD (402) is adapted to communicate with and receive power from the PSE via the cable, in accordance with the Power-over-Ethernet (PoE) standard. The PD (402) extracts (413) from the cable (408) a DC signal used to power the PD without using a transformer. Capacitors (420) located in the signal paths between the MAC (419) and the cable (408) support electrical isolation of the MAC (419).Type: ApplicationFiled: June 16, 2006Publication date: August 26, 2010Applicant: AGERE SYSTEMS INC.Inventors: Matthew Blaha, Luis de La Torre, Alan L. Ellis, Gary D. Polhemus, Patrick J. Quirk
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Patent number: 7774584Abstract: The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106) and a general purpose host central processing unit (CPU 102). The DSP (106) handles all front end data pump processing such as interface to an analog front end (108 and 110), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU (102) handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP (106) and the CPU (102) to communicate with each other effectively, buffers (132) under the control of specialized buffer management methodology (FIG. 4) are used.Type: GrantFiled: June 27, 2007Date of Patent: August 10, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Charles E. Polk, Jr., Lee T. Gusler, Patrick J. Quirk, Ronald M. Zuckerman, Joe L. Wilson, Jr.
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Patent number: 7685440Abstract: In one embodiment, the invention is an apparatus (e.g., an Ethernet switch) having an isolated side and a line side. A line-side connector is connectable to a cable. An isolated-side physical-layer module (1) is electrically coupled to the connector via a signal-isolation transformer and (2) processes signals transmitted over the cable. A line-side power conditioning module (1) is electrically coupled to an isolated-side power switcher via a power-isolation transformer that converts an AC power signal received from the power switcher into a transformed AC power signal and (2) converts the transformed AC power signal into a cable power signal to be supplied via the connector to the cable in order to power a cable-powered device connected to the cable. An isolated-side control module performs a detection function in which the control module determines whether or not a cable-powered device is connected to the cable.Type: GrantFiled: March 6, 2006Date of Patent: March 23, 2010Assignee: Agere Systems Inc.Inventors: Matthew Blaha, Patrick J. Quirk
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Patent number: 7643315Abstract: Disclosed is a method and apparatus that includes a power supply having a primary coil and a secondary coil. The secondary coil generates an output voltage and a feedback voltage related to the output voltage. The feedback voltage is sampled at a time instant that is digitally controllable. The output voltage is determined from the feedback voltage.Type: GrantFiled: November 19, 2008Date of Patent: January 5, 2010Assignee: Agere Systems, Inc.Inventors: Matthew Blaha, Albert Molina, Patrick J. Quirk, Fadi Saibi
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Publication number: 20090073734Abstract: Disclosed is a method and apparatus that includes a power supply having a primary coil and a secondary coil. The secondary coil generates an output voltage and a feedback voltage related to the output voltage. The feedback voltage is sampled at a time instant that is digitally controllable. The output voltage is determined from the feedback voltage.Type: ApplicationFiled: November 19, 2008Publication date: March 19, 2009Inventors: Mathew Blaha, Albert Molina, Patrick J. Quirk, Fadi Saibi
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Patent number: 7471531Abstract: Disclosed is a method and apparatus that includes a power supply having a primary coil and a secondary coil. The secondary coil generates an output voltage and a feedback voltage related to the output voltage. The feedback voltage is sampled at a time instant that is digitally controllable. The output voltage is determined from the feedback voltage.Type: GrantFiled: August 22, 2006Date of Patent: December 30, 2008Assignee: Agere Systems Inc.Inventors: Matthew Blaha, Albert Molina, Patrick J. Quirk, Fadi Saibi
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Publication number: 20080080105Abstract: One embodiment monitors a line-side electrical current provided by a power sourcing equipment (PSE) port to a powered device (PD), the PSE port having a power-isolation transformer with a primary coil on an isolated side and a secondary coil on a line side. A switching signal having a switching period and a duty cycle is applied to the primary coil of the power-isolation transformer. A value is determined for an electrical current on the isolated side of the power-isolation transformer, conversion is performed between a line-side electrical current value Iout and a corresponding isolated-side peak-current value Ipeak, and the line-side electrical current is indirectly monitored based on the determined isolated-side current value.Type: ApplicationFiled: September 29, 2006Publication date: April 3, 2008Applicant: AGERE SYSTEMS INC.Inventors: Matthew Blaha, Luis de la Torre, Patrick J. Quirk, Fadi Saibi
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Publication number: 20080049459Abstract: Disclosed is a method and apparatus that includes a power supply having a primary coil and a secondary coil. The secondary coil generates an output voltage and a feedback voltage related to the output voltage. The feedback voltage is sampled at a time instant that is digitally controllable. The output voltage is determined from the feedback voltage.Type: ApplicationFiled: August 22, 2006Publication date: February 28, 2008Inventors: Matthew Blaha, Albert Molina, Patrick J. Quirk, Fadi Saibi
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Patent number: 7254766Abstract: The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106) and a general purpose host central processing unit (CPU 102). The DSP (106) handles all front end data pump processing such as interface to an analog front end (108 and 110), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU (102) handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP (106) and the CPU (102) to communicate with each other effectively, buffers (132) under the control of specialized buffer management methodology (FIG. 4) are used.Type: GrantFiled: March 30, 2005Date of Patent: August 7, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Charles E. Polk, Jr., Lee T. Gusler, Patrick J. Quirk, Ronald M. Zuckerman, Joe L. Wilson, Jr.
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Patent number: 6892339Abstract: The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106) and a general purpose host central processing unit (CPU 102). The DSP (106) handles all front end data pump processing such as interface to an analog front end (108 and 110), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU (102) handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP (106) and the CPU (102) to communicate with each other effectively, buffers (132) under the control of specialized buffer management methodology (FIG. 4) are used.Type: GrantFiled: September 20, 1999Date of Patent: May 10, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Charles E. Polk, Jr., Lee T. Gusler, Patrick J. Quirk, Ronald M. Zuckerman, Joe L. Wilson, Jr.
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Patent number: 6052409Abstract: In a digital communication device adapted to be coupled to a digital network and having an analog port adapted for interconnecting an analog device to the digital communication device, a device for generating and detecting tones, includes: a processor programmed to selectively generate one of a first set of digital tones in a generation mode and to detect one of a second set of digital tones in a detection mode; and a conversion circuit, operably coupled to the processor, adapted to convert the one of the first set of digital tones generated by the processor in the generation mode to an analog tone and transmit the analog tone to the analog device; the conversion circuit further being adapted to convert an analog tone received from the analog device to the one of the second set of digital tones and transmit the digital tone to the processor when the processor is in the detection mode.Type: GrantFiled: April 30, 1997Date of Patent: April 18, 2000Assignee: Motorola Inc.Inventors: Patrick J. Quirk, Todd W. Lumpkin, Christian Paul Nelson