Abstract: The present disclosure provides for a modular design and build architecture, comprising: one or more integrated system module (ISMs) that are configured to be shipped and assembled on-site to construct an operational infrastructure for one or more application environments, wherein each of the ISMs comprises two or more different functional components that are integrated onto and/or supported by a common structural floor.

Abstract: The present disclosure provides for a modular design and build architecture, comprising: one or more integrated system module (ISMs) that are configured to be shipped and assembled on-site to construct an operational infrastructure for one or more application environments, wherein each of the ISMs comprises two or more different functional components that are integrated onto and/or supported by a common structural floor.

Abstract: The present disclosure provides for a modular design and build architecture, comprising: one or more integrated system module (ISMs) that are configured to be shipped and assembled on-site to construct an operational infrastructure for one or more application environments, wherein each of the ISMs comprises two or more different functional components that are integrated onto and/or supported by a common structural floor.

Abstract: The present disclosure provides for a modular design and build architecture, comprising: one or more integrated system module (ISMs) that are configured to be shipped and assembled on-site to construct an operational infrastructure for one or more application environments, wherein each of the ISMs comprises two or more different functional components that are integrated onto and/or supported by a common structural floor.

Abstract: In one embodiment, a powered device (PD) (402) has a PHY module (410) and a media access controller (419) (MAC), the PD (402) adapted to connect to power sourcing equipment (PSE) via a cable, (408) where the PD (402) is adapted to communicate with and receive power from the PSE via the cable, in accordance with the Power-over-Ethernet (PoE) standard. The PD (402) extracts (413) from the cable (408) a DC signal used to power the PD without using a transformer. Capacitors (420) located in the signal paths between the MAC (419) and the cable (408) support electrical isolation of the MAC (419).

Abstract: One embodiment monitors a line-side electrical current provided by a power sourcing equipment (PSE) port to a powered device (PD), the PSE port having a power-isolation transformer with a primary coil on an isolated side and a secondary coil on a line side. A switching signal having a switching period and a duty cycle is applied to the primary coil of the power-isolation transformer. A value is determined for an electrical current on the isolated side of the power-isolation transformer, conversion is performed between a line-side electrical current value Iout and a corresponding isolated-side peak-current value Ipeak, and the line-side electrical current is indirectly monitored based on the determined isolated-side current value.

Abstract: In one embodiment, a powered device (PD) (402) has a PHY module (410) and a media access controller (419) (MAC), the PD (402) adapted to connect to power sourcing equipment (PSE) via a cable, (408) where the PD (402) is adapted to communicate with and receive power from the PSE via the cable, in accordance with the Power-over-Ethernet (PoE) standard. The PD (402) extracts (413) from the cable (408) a DC signal used to power the PD without using a transformer. Capacitors (420) located in the signal paths between the MAC (419) and the cable (408) support electrical isolation of the MAC (419).

Abstract: The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106) and a general purpose host central processing unit (CPU 102). The DSP (106) handles all front end data pump processing such as interface to an analog front end (108 and 110), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU (102) handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP (106) and the CPU (102) to communicate with each other effectively, buffers (132) under the control of specialized buffer management methodology (FIG. 4) are used.

Abstract: In one embodiment, the invention is an apparatus (e.g., an Ethernet switch) having an isolated side and a line side. A line-side connector is connectable to a cable. An isolated-side physical-layer module (1) is electrically coupled to the connector via a signal-isolation transformer and (2) processes signals transmitted over the cable. A line-side power conditioning module (1) is electrically coupled to an isolated-side power switcher via a power-isolation transformer that converts an AC power signal received from the power switcher into a transformed AC power signal and (2) converts the transformed AC power signal into a cable power signal to be supplied via the connector to the cable in order to power a cable-powered device connected to the cable. An isolated-side control module performs a detection function in which the control module determines whether or not a cable-powered device is connected to the cable.

Abstract: Disclosed is a method and apparatus that includes a power supply having a primary coil and a secondary coil. The secondary coil generates an output voltage and a feedback voltage related to the output voltage. The feedback voltage is sampled at a time instant that is digitally controllable. The output voltage is determined from the feedback voltage.

Abstract: Disclosed is a method and apparatus that includes a power supply having a primary coil and a secondary coil. The secondary coil generates an output voltage and a feedback voltage related to the output voltage. The feedback voltage is sampled at a time instant that is digitally controllable. The output voltage is determined from the feedback voltage.

Abstract: Disclosed is a method and apparatus that includes a power supply having a primary coil and a secondary coil. The secondary coil generates an output voltage and a feedback voltage related to the output voltage. The feedback voltage is sampled at a time instant that is digitally controllable. The output voltage is determined from the feedback voltage.

Abstract: One embodiment monitors a line-side electrical current provided by a power sourcing equipment (PSE) port to a powered device (PD), the PSE port having a power-isolation transformer with a primary coil on an isolated side and a secondary coil on a line side. A switching signal having a switching period and a duty cycle is applied to the primary coil of the power-isolation transformer. A value is determined for an electrical current on the isolated side of the power-isolation transformer, conversion is performed between a line-side electrical current value Iout and a corresponding isolated-side peak-current value Ipeak, and the line-side electrical current is indirectly monitored based on the determined isolated-side current value.

Abstract: Disclosed is a method and apparatus that includes a power supply having a primary coil and a secondary coil. The secondary coil generates an output voltage and a feedback voltage related to the output voltage. The feedback voltage is sampled at a time instant that is digitally controllable. The output voltage is determined from the feedback voltage.

Abstract: The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106) and a general purpose host central processing unit (CPU 102). The DSP (106) handles all front end data pump processing such as interface to an analog front end (108 and 110), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU (102) handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP (106) and the CPU (102) to communicate with each other effectively, buffers (132) under the control of specialized buffer management methodology (FIG. 4) are used.

Abstract: The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106) and a general purpose host central processing unit (CPU 102). The DSP (106) handles all front end data pump processing such as interface to an analog front end (108 and 110), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU (102) handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP (106) and the CPU (102) to communicate with each other effectively, buffers (132) under the control of specialized buffer management methodology (FIG. 4) are used.

Abstract: In a digital communication device adapted to be coupled to a digital network and having an analog port adapted for interconnecting an analog device to the digital communication device, a device for generating and detecting tones, includes: a processor programmed to selectively generate one of a first set of digital tones in a generation mode and to detect one of a second set of digital tones in a detection mode; and a conversion circuit, operably coupled to the processor, adapted to convert the one of the first set of digital tones generated by the processor in the generation mode to an analog tone and transmit the analog tone to the analog device; the conversion circuit further being adapted to convert an analog tone received from the analog device to the one of the second set of digital tones and transmit the digital tone to the processor when the processor is in the detection mode.

Abstract: The apparatus and method for high speed data and command transfer over an interface (202), such as an ISA or PCMCIA bus or interface, includes a transceiver (206) and a processor (210) having a direct memory access (DMA) controller (240), a memory (211) for storage of data, and a channel interface (218) for connection to a communications channel. The processor (210) is responsive through a set of program instructions, such as software or firmware, to receive an interrupt signal (310, 315) and, when the interrupt signal indicates a write command (320, 330), to transfer data via the transceiver from the interface to the memory for transmission over the communications channel (335), and when the interrupt signal indicates data received from the communications channel (350), the processor further responsive to generate a read command and transfer data from the memory to the interface via the transceiver (355).

Abstract: A method to encode and to decode frames of data used in synchronous protocols, including HDLC and SDLC. The invention operates on blocks of data, such as data bytes or data words, in a parallel rather than a bit serial manner. The invention compares an aligned block of data with reference bit sequences for flag or abort signal detection, for zero detection, for zero deletion, for detection of consecutive one bits, and for zero insertion following a stream of consecutive one bits, for encoding and decoding according to various protocols. The invention also maintains proper data alignment following such zero insertions or deletions, and provides encoding and decoding under both data overrun and data underrun conditions.