Patents by Inventor Patrick James Lee

Patrick James Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6292912
    Abstract: A disk drive has a normal mode of operation and a built-in self-test (BIST) mode of operation for producing a sequence of channel metrics {&Ggr;n}. The disk drive includes a recording surface having a plurality of bit cells and a transducer for reading the plurality of bit cells to produce a noise-corrupted read signal. The disk drive further includes means responsive to the noise-corrupted read signal for generating a sequence of observed samples {yn}, the sequence of observed samples {yn} forming a sequence of observed-sample subsequences {Yn}. An expected sample generator operates during the BIST mode of operation to provide a sequence of expected samples {wn}, the sequence of expected samples forming a sequence of expected-sample subsequences {Wn}. A channel metrics &Ggr;n computation system computes a sequence of channel metrics {&Ggr;n}.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: September 18, 2001
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert Leslie Cloke, Patrick James Lee, Howard Anthony Baumer
  • Patent number: 6246346
    Abstract: A storage system employs a method for encoding a sequence of input data blocks into a sequence of codewords. Each input data block includes a first predetermined number of bits (the data block length). Each codeword includes a second predetermined number of bits (the codeword length). The code rate, i.e., the ratio of the first number to the second number, is greater than ¾. The method is performed in a sampled-data channel in a storage system; and the channel includes a circuit the performance of which is adversely affected by an excessive run length of bits between occurrences of a predetermined influential pattern. Preferably, the influential pattern is a two-bit sequence of adjacent 1's, which favorably influences the performance of a timing recovery circuit. The method includes receiving the sequence of input data blocks and generating the sequence of codewords responsive to the received sequence of input data blocks.
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: June 12, 2001
    Assignee: Western Digital Corporation
    Inventors: Robert Leslie Cloke, Patrick James Lee, Steven William McLaughlin
  • Patent number: 6208477
    Abstract: In a hard disk drive, a semiconductor chip includes a circuit used in a built-in self test (“BIST”) to determine an amplitude of a dibit echo for characterizing nonlinear distortion of a readback signal. Preferably, write precompensation is performed based on results of the BIST to minimize distortion attributable to intersymbol interference. A generator is used to generate a maximal length pseudo-random sequence. This maximal length pseudo-random sequence is input to a correlator which performs a correlation between the maximal length pseudo-random bit sequence and a readback signal responsive to the pseudo-random sequence that was stored onto a disk of the hard disk drive. In one embodiment, a seed value stored in memory is loaded into the generator upon detection of a synchronization signal read from the disk. With the appropriate seed value loaded into the generator, a specific pseudo-random bit sequence corresponding to a sample point of interest is then generated.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: March 27, 2001
    Assignee: Western Digital Corporation
    Inventors: Robert Leslie Cloke, Patrick James Lee
  • Patent number: 5822143
    Abstract: A partial-response maximum-likelihood (PRML) sequence detector with decision feedback equalization (DFE) for a disk drive read channel. The symbol recovery method for a disk drive read channel produces a sequence of samples X.sub.n of a magnetic readback signal with amplitudes representing the readback signal during corresponding sample intervals n=1-N. A DFE circuit generates a sequence of equalized samples y.sub.n and includes a feed-forward filter that removes precursor ISI from the sequence of sample signals x.sub.n to produce a sequence of feed-forward equalized samples w.sub.n, detection logic that translates the sequence of equalized samples y.sub.n into a sequence of detected symbols y.sub.n, and a feedback filter that filters the sequence of detected symbols y.sub.n to produce a sequence of equalization feedback values e.sub.n to offset postcursor ISI remaining in the sequence of feed-forward equalized samples w.sub.n. A combinational circuit receives the feed-forward equalized samples w.sub.
    Type: Grant
    Filed: June 11, 1996
    Date of Patent: October 13, 1998
    Assignee: Western Digital Corporation
    Inventors: Robert Leslie Cloke, Patrick James Lee