Patents by Inventor Patrick James McGuinness

Patrick James McGuinness has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SPARK GAPS WITH MULTIPLE TRIGGER VOLTAGES FOR ELECTRICAL OVERSTRESS DETECTION AND PROTECTION
    Publication number: 20250030237
    Abstract: Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a vertical spark gap device includes a substrate having a horizontal main surface and a plurality of pairs of conductive layers over the horizontal main surface. Different ones of the pairs are separated by different vertical distances such that each pair serves as an arcing electrode pair and different ones of the arcing electrode pairs are configured to arc discharge at different voltages.
    Type: Application
    Filed: May 30, 2024
    Publication date: January 23, 2025
    Inventors: David J. Clarke, Alan J. O'Donnell, Shaun Stephen Bradley, Stephen Denis Heffernan, Patrick Martin McGuinness, Padraig L. Fitzgerald, Edward John Coyne, Michael P. Lynch, John Anthony Cleary, John Ross Wallrabenstein, Paul Joseph Maher, Andrew Christopher Linehan, Gavin Patrick Cosgrave, Michael James Twohig, Jan Kubik, Jochen Schmitt, David Aherne, Mary McSherry, Anne M. McMahon, Stanislav Jolondcovschi, Cillian Burke
  • Method for automated transistor folding
    Patent number: 7124385
    Abstract: A method for generating an integrated circuit layout is disclosed. One embodiment includes receiving an integrated circuit netlist describing a plurality of transistors and a plurality of conductors for interconnecting the plurality of transistors, each of the plurality of transistors having a width in a layout corresponding to the integrated circuit netlist. More than one of the plurality of transistors are determined to be the widest transistors, all having the same width. One of the widest transistors is folded to produce a folded transistor that is electrically equivalent to the widest transistor. The folded transistor has at least two fingers, each finger having a smaller width than the width of the widest transistors. A fold solution for the layout having the one folded transistor is created.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: October 17, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Patrick James McGuinness, Robert Lee Maziasz, Andrei Vladimirovitch Zinchenko, Vladimir Pavlovich Rozenfeld, Michael Viacheslavovich Golikov, Alexander Mikhailovich Marchenko
  • Apparatus and method for automated transistor and component folding to produce cell structures
    Publication number: 20040078768
    Abstract: A method for generating an integrated circuit layout is disclosed. One embodiment includes receiving an integrated circuit netlist describing a plurality of transistors and a plurality of conductors for interconnecting the plurality of transistors, each of the plurality of transistors having a width in a layout corresponding to the integrated circuit netlist. More than one of the plurality of transistors are determined to be the widest transistors, all having the same width. One of the widest transistors is folded to produce a folded transistor that is electrically equivalent to the widest transistor. The folded transistor has at least two fingers, each finger having a smaller width than the width of the widest transistors. A fold solution for the layout having the one folded transistor is created.
    Type: Application
    Filed: September 8, 2003
    Publication date: April 22, 2004
    Inventors: Patrick James McGuinness, Robert Lee Maziasz, Andrei Vladimirovitch Zinchenko, Vladimir Pavlovich Rozenfeld, Michael Viacheslavovich Golikov, Alexander Mikhailovich Marchenko