Abstract: Dynamic key reassignment for memory encryption keys, including: performing a key reassignment for a memory area by, for each memory address of a plurality of memory addresses in the memory area: reading data from a selected memory address by decrypting the data using a first encryption key stored in a first encryption key register, wherein the selected memory address is stored in a scrub address register incremented after each iteration of the key reassignment; and writing the data to the selected memory address by encrypting the data using a second encryption key stored in a second encryption key register.

Abstract: In some implementations, a controller may determine that a read response, to a read command of a plurality of read commands, has not been received from a memory device of a plurality of memory devices. The controller may provide a cancel command to the memory device to cause the memory device to cancel the read command based on determining that the read response, to the read command, has not been received from the memory device, wherein the cancel command is provided after read responses, to other read commands of the plurality of read commands, have been received from other memory devices of the plurality of memory devices, and wherein the cancel command includes an identifier associated with the read command.

Abstract: Described is a method for monitoring and rotating electrical and/or mechanical components, the method includes receiving a set of metrics for a plurality of components and evaluating the set of metrics for the plurality of components. The method also includes determining to perform a component rotation for a first component from the plurality of components and performing a component rotation based on a component rotation plan, where the component rotation plan indicates the first component from the plurality of components is to be rotated with a second component from the plurality of components.

Abstract: A computer system, computer readable storage medium, and computer-implemented method for dynamically degrading a link between multiple processing devices to facilitate uninterrupted service between the multiple processing devices. The method includes determining a number of undegraded lanes within the link. The method also includes determining, subject to the number of undegraded lanes, a first operational degrade mode for the link. The method further includes initiating a retrain of the link to a second operational degrade mode. The method also includes dynamically, subject to the first degrade mode of operation, determining one or more message packet types to transmit through the link during the link retrain, thereby facilitating uninterrupted service between the multiple processing devices.

Abstract: Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

Abstract: Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

Abstract: A computer system, computer readable storage medium, and computer-implemented method for dynamically degrading a link between multiple processing devices to facilitate uninterrupted service between the multiple processing devices. The method includes determining a number of undegraded lanes within the link. The method also includes determining, subject to the number of undegraded lanes, a first operational degrade mode for the link. The method further includes initiating a retrain of the link to a second operational degrade mode. The method also includes dynamically, subject to the first degrade mode of operation, determining one or more message packet types to transmit through the link during the link retrain, thereby facilitating uninterrupted service between the multiple processing devices.

Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.

Abstract: A memory controller stores each of a plurality of data blocks encoded by error correction code (ECC) across multiple channels of a redundant memory system. Based on receiving, from the memory system, channel data of a fetch operation requesting a data block, the memory controller decodes the channel data and concurrently generates a predicted channel mark based on tests of channel-induced syndromes generated from the channel data. The predicted channel mark identifies a marked channel among the multiple channels as a likely source of data errors. The memory controller determines whether the decoding detects an uncorrectable error in the channel data and, based on determining the decoding detects an uncorrectable error in the channel data, re-reads channel data corresponding to the data block and corrects the re-read channel data by excluding, from decoding, channel data received from the marked channel.

Abstract: Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.

Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.

Abstract: A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.

Abstract: Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.

Abstract: A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.

Abstract: A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.

Abstract: A computer-implemented method includes refreshing a set of memory channels in a memory system substantially simultaneously, each memory channel refreshing a rank that is distinct from each of the other ranks being refreshed. Further, the method includes marking a memory channel from the set of memory channels as being unavailable for the rank being refreshed in the memory channel. In one or more examples, the method further includes blocking a fetch command to the memory channel for the rank being refreshed in the memory channel.

Abstract: A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.

Abstract: A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.

Abstract: A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.

Abstract: A computer-implemented method includes refreshing a set of memory channels in a memory system substantially simultaneously, each memory channel refreshing a rank that is distinct from each of the other ranks being refreshed. Further, the method includes marking a memory channel from the set of memory channels as being unavailable for the rank being refreshed in the memory channel. In one or more examples, the method further includes blocking a fetch command to the memory channel for the rank being refreshed in the memory channel.