Patents by Inventor Patrick James Meaney
Patrick James Meaney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960426Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.Type: GrantFiled: June 1, 2022Date of Patent: April 16, 2024Assignee: International Business Machines CorporationInventors: Rajat Rao, Patrick James Meaney, Glenn David Gilda, Michael Jason Cade, Robert J Sonnelitter, III, Hubert Harrer, Xiaomin Duan, Christian Jacobi, Arthur O'Neill
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Publication number: 20240103967Abstract: A memory controller stores each of a plurality of data blocks encoded by error correction code (ECC) across multiple channels of a redundant memory system. Based on receiving, from the memory system, channel data of a fetch operation requesting a data block, the memory controller decodes the channel data and concurrently generates a predicted channel mark based on tests of channel-induced syndromes generated from the channel data. The predicted channel mark identifies a marked channel among the multiple channels as a likely source of data errors. The memory controller determines whether the decoding detects an uncorrectable error in the channel data and, based on determining the decoding detects an uncorrectable error in the channel data, re-reads channel data corresponding to the data block and corrects the re-read channel data by excluding, from decoding, channel data received from the marked channel.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Inventors: Barry M. Trager, Patrick James Meaney, Glenn David Gilda, Lawrence Jones
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Patent number: 11907074Abstract: Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.Type: GrantFiled: September 24, 2021Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Patrick James Meaney, Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan Ian Friedman, Jentje Leenstra, Glenn David Gilda, Michael B. Spear
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Publication number: 20230393999Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.Type: ApplicationFiled: June 1, 2022Publication date: December 7, 2023Inventors: Rajat Rao, Patrick James Meaney, Glenn David Gilda, Michael Jason Cade, Robert J Sonnelitter, III, Hubert Harrer, Xiaomin Duan, Christian Jacobi, Arthur O'Neill
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Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes
Patent number: 11646861Abstract: A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.Type: GrantFiled: September 24, 2021Date of Patent: May 9, 2023Assignee: International Business Machines CorporationInventors: Patrick James Meaney, Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan Ian Friedman, Jentje Leenstra, Glenn David Gilda, Jason Andrew Thompson, Yvonne Hanson Kleppel -
Publication number: 20230115533Abstract: Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.Type: ApplicationFiled: September 24, 2021Publication date: April 13, 2023Inventors: Patrick James Meaney, Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan Ian Friedman, Jentje Leenstra, Glenn David Gilda, Michael B. Spear
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LOW-LATENCY, HIGH-AVAILABILITY AND HIGH-SPEED SERDES INTERFACE HAVING MULTIPLE SYNCHRONIZATION MODES
Publication number: 20230098514Abstract: A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Patrick James Meaney, Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan Ian Friedman, Jentje Leenstra, Glenn David Gilda, Jason Andrew Thompson, Yvonne Hanson Kleppel -
Patent number: 11609817Abstract: A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.Type: GrantFiled: September 9, 2021Date of Patent: March 21, 2023Assignee: International Business Machines CorporationInventors: Patrick James Meaney, Glenn David Gilda, David D. Cadigan, Lawrence Jones
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Patent number: 11520659Abstract: A computer-implemented method includes refreshing a set of memory channels in a memory system substantially simultaneously, each memory channel refreshing a rank that is distinct from each of the other ranks being refreshed. Further, the method includes marking a memory channel from the set of memory channels as being unavailable for the rank being refreshed in the memory channel. In one or more examples, the method further includes blocking a fetch command to the memory channel for the rank being refreshed in the memory channel.Type: GrantFiled: January 13, 2020Date of Patent: December 6, 2022Assignee: International Business Machines CorporationInventors: Patrick James Meaney, Glenn David Gilda, David D. Cadigan, Christian Jacobi, Lawrence Jones, Stephen J. Powell
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Publication number: 20210406126Abstract: A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.Type: ApplicationFiled: September 9, 2021Publication date: December 30, 2021Inventors: Patrick James MEANEY, Glenn David GILDA, David D. CADIGAN, Lawrence JONES
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Patent number: 11200119Abstract: A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.Type: GrantFiled: January 13, 2020Date of Patent: December 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Patrick James Meaney, Glenn David Gilda, David D. Cadigan, Lawrence Jones
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Publication number: 20210216400Abstract: A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.Type: ApplicationFiled: January 13, 2020Publication date: July 15, 2021Inventors: PATRICK JAMES MEANEY, GLENN DAVID GILDA, DAVID D. CADIGAN, LAWRENCE JONES
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Publication number: 20210216401Abstract: A computer-implemented method includes refreshing a set of memory channels in a memory system substantially simultaneously, each memory channel refreshing a rank that is distinct from each of the other ranks being refreshed. Further, the method includes marking a memory channel from the set of memory channels as being unavailable for the rank being refreshed in the memory channel. In one or more examples, the method further includes blocking a fetch command to the memory channel for the rank being refreshed in the memory channel.Type: ApplicationFiled: January 13, 2020Publication date: July 15, 2021Inventors: PATRICK JAMES MEANEY, GLENN DAVID GILDA, DAVID D. CADIGAN, CHRISTIAN JACOBI, LAWRENCE JONES, STEPHEN J. POWELL
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Patent number: 7987400Abstract: A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.Type: GrantFiled: February 22, 2008Date of Patent: July 26, 2011Assignee: International Business Machines CorporationInventors: Christopher J. Berry, Lawrence David Curley, Patrick James Meaney, Diana Lynn Orf
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Patent number: 7979838Abstract: The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.Type: GrantFiled: February 15, 2008Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Christopher J. Berry, Jose Luis Pontes Correia Neves, Lawrence David Curley, Patrick James Meaney, Travis Wellington Pouarz, William J. Scarpero, Jr.
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Patent number: 7702972Abstract: SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM macro to be shut off and replaced by a spare macro, dramatically increasing manufacturing yield and decreasing field replacement rates. The larger the protected group, the fewer the number of spares required for similar improvements in yield, but also the more difficult the task of making all the controls and dataflow available to the spare(s). In the case of the Level 2 Cache chip for the planned IBM Z6 computer, there are 4 protected groups with 192 SRAM macros per group. Each protected group is supplanted with an additional 2 spare SRAM macros, along with sparing controls and dataflow that allow either spare to replace any of the 192 protected SRAM macros.Type: GrantFiled: October 18, 2007Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: Timothy Carl Bronson, Garrett Drapala, Hieu Trong Huynh, Patrick James Meaney
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Publication number: 20090217115Abstract: A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.Type: ApplicationFiled: February 22, 2008Publication date: August 27, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Berry, Lawrence David Curley, Patrick James Meaney, Diana Lynn Orf
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Publication number: 20090210843Abstract: The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.Type: ApplicationFiled: February 15, 2008Publication date: August 20, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Berry, Jose Luis Ponters Correia Neves, Lawrence David Curley, Patrick James Meaney, Travis Wellington Pouarz, William J. Scarpero, JR.
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Publication number: 20090106607Abstract: SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM macro to be shut off and replaced by a spare macro, dramatically increasing manufacturing yield and decreasing field replacement rates. The larger the protected group, the fewer the number of spares required for similar improvements in yield, but also the more difficult the task of making all the controls and dataflow available to the spare(s). In the case of the Level 2 Cache chip for the planned IBM Z6 computer, there are 4 protected groups with 192 SRAM macros per group. Each protected group is supplanted with an additional 2 spare SRAM macros, along with sparing controls and dataflow that allow either spare to replace any of the 192 protected SRAM macros.Type: ApplicationFiled: October 18, 2007Publication date: April 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Carl Bronson, Garrett Drapala, Hieu Trong Huynh, Patrick James Meaney
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Patent number: 6195757Abstract: A system for improving system cycle time while supporting 1½ cycle data paths with a PLL based clock system using a communication circuit providing a first mode of operation whereby a first cycle time is obtained, and for allowing use of a second mode of operation whereby a second longer multi-mode cycle time is obtained to extend the time for evaluation of data on the bi-directional data path between a first chip and a memory circuit.Type: GrantFiled: January 26, 1998Date of Patent: February 27, 2001Assignee: International Business Machine CorporationInventors: Timothy Gerard McNamara, Patrick James Meaney, Paul David Muench, Giacomo Vincent Ingenio