Patents by Inventor Patrick Jerier

Patrick Jerier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic
    Patent number: 6776842
    Abstract: The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: August 17, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Didier Dutartre, Patrick Jerier
  • Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic
    Publication number: 20020081374
    Abstract: The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.
    Type: Application
    Filed: January 15, 2002
    Publication date: June 27, 2002
    Applicant: STMicroelectronics S.A.
    Inventors: Didier Dutartre, Patrick Jerier
  • Method of epitaxy on a silicon substrate comprising areas heavily doped with boron
    Patent number: 6294443
    Abstract: A method of vapor phase epitaxy deposition of silicon on a silicon substrate on or in which exist areas containing dopants at high concentration, among which is boron, while avoiding a selfdoping of the epitaxial layer by boron, including the step of introducing a chlorinated gas, before the epitaxial deposition step, to etch the substrate across a thickness smaller than 100 nm.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: September 25, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Didier Dutartre, Patrick Jerier
  • Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic
    Patent number: 6162706
    Abstract: The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: December 19, 2000
    Assignee: STMicroelectronics S.A.
    Inventors: Didier Dutartre, Patrick Jerier