Abstract: Various embodiments provide apparatuses, systems, and methods for automatic phase scaling (APS) of dynamic voltage ID (DVID) in a voltage regulator. Other embodiments may be described and claimed.

Abstract: Power management circuitry may be provided to control a power state of a voltage regulator for providing a regulated voltage to a load, the voltage regulator being operable in at least first and second different power states. The power management circuitry may comprise circuitry to determine output current data relating to an output current to be provided by the voltage regulator to the load. The power management circuitry may comprise circuitry to determine regulated voltage data relating to a regulated voltage to be provided by the voltage regulator to the load. The power management circuitry may comprise circuitry to cause a change in the power state of the voltage regulator from the first power state to the second power state based on a comparison of the determined output current data and power state current threshold data.

Abstract: In one embodiment, a processor includes: at least one core to execute a workload; a voltage regulator to provide an operating voltage to the at least one core; and a power controller coupled to the voltage regulator. The power controller may control the voltage regulator to provide the operating voltage, and may have a voltage regulator control circuit to select one of a plurality of power state profiles based at least in part on a classification of the workload, and to cause an update to a power state of the voltage regulator according to the selected power state profile. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes: at least one core to execute a workload; a voltage regulator to provide an operating voltage to the at least one core; and a power controller coupled to the voltage regulator. The power controller may control the voltage regulator to provide the operating voltage, and may have a voltage regulator control circuit to select one of a plurality of power state profiles based at least in part on a classification of the workload, and to cause an update to a power state of the voltage regulator according to the selected power state profile. Other embodiments are described and claimed.

Abstract: In one embodiment, a method receives data regarding processing of a workload by a processor. The data is input into a prediction engine configured to classify the data into a plurality of workload classifications. Each workload classification describes different temporal behavior of the workload. Then, the method outputs a prediction for at least one of the plurality of workload classifications, wherein the prediction is used to control performance of the processor in an upcoming period of time.

Abstract: In one embodiment, a processor includes: at least one core to execute a workload; a voltage regulator to provide an operating voltage to the at least one core; and a power controller coupled to the voltage regulator. The power controller may control the voltage regulator to provide the operating voltage, and may have a voltage regulator control circuit to select one of a plurality of power state profiles based at least in part on a classification of the workload, and to cause an update to a power state of the voltage regulator according to the selected power state profile. Other embodiments are described and claimed.

Abstract: In one embodiment, a method receives data regarding processing of a workload by a processor. The data is input into a prediction engine configured to classify the data into a plurality of workload classifications. Each workload classification describes different temporal behavior of the workload. Then, the method outputs a prediction for at least one of the plurality of workload classifications, wherein the prediction is used to control performance of the processor in an upcoming period of time.

Abstract: A method and system are disclosed for simulating a direct memory access (DMA) function to access memory in a host computer having a DMA controller for the purpose of enabling the transfer of data between the host memory and a computer accessory data handling device not capable of DMA operation. The accessory data handling device can be operably connected to the host. The address contents of the DMA controller can be read to determine the location in the host memory where data is to be transferred from the host memory to the accessory data handling device or from the accessory data handling device to the host memory. Data is read from the host memory at the address specified in the DMA controller and written to the accessory data handling device or read from the accessory data handling device and written to the host memory at the address specified by the DMA controller, respectively.