Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell; performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell; performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell.

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving data to be stored on the memory device, storing a first copy of the data in a first set of memory cells of the memory device, and storing a second copy of the data in a second set of memory cells of the memory device. The operations can also include reading the first copy of the data and determining whether a threshold voltage of a cell in the first set of memory cells is within an overlapping range of voltage distributions, and reading the second copy of the data and determining whether the threshold voltage of a cell in the second set of memory cells is within an overlapping range of voltage distributions. They can also include using the second copy of the data.

Abstract: A system for decoding data includes a symbol based error correction code device. The error correction code device includes a channel detector configured to generate probability mass function (PMF) information. The error correction code device further includes a decoder coupled to the channel detector. The decoder is configured to use the PMF information from the channel detector to perform an error correction code operation. The decoder also is configured to generate PMF information. The channel detector is configured to receive extrinsic PMF information in a turbo equalization scheme.

Abstract: A system for decoding data includes a symbol based error correction code device. The error correction code device includes a channel detector configured to generate probability mass function (PMF) information. The error correction code device further includes a decoder coupled to the channel detector. The decoder is configured to use the PMF information from the channel detector to perform an error correction code operation. The decoder also is configured to generate PMF information. The channel detector is configured to receive extrinsic PMF information in a turbo equalization scheme.