Abstract: A computing system is associated with power consumption based on Power over Ethernet (PoE). Power consumption is compared to a threshold, and a signal is asserted that power consumption is to be limited based on the comparison to the threshold.

Abstract: A computing system is associated with power consumption based on Power over Ethernet (PoE). Power consumption is compared to a threshold, and a signal is asserted that power consumption is to be limited based on the comparison to the threshold.

Abstract: A computing system is associated with power consumption based on Power over Ethernet (PoE). Power consumption is compared to a threshold, and a signal is asserted that power consumption is to be limited based on the comparison to the threshold.

Abstract: Electronic circuits and methods are provided for conserving power within computers and other apparatus. A logic circuit performs a logical operation on a plurality of variables thus deriving a corresponding output. The output is used to drive and maintain an open or closed state of an electronic switch, accordingly. The electronic switch is disposed between a source of electrical energy and a system power buss of a computer. The computer can assume very low power, full power and other respective operating modes in accordance with the present state of the electronic switch.

Abstract: A first resistance (125) within a power supply (110) can be connected to a power supply output (120). A variable resistance (130) can be serially coupled with the first resistance, thereby providing a first intermediate voltage at a point (115) disposed between the first resistance and the variable resistance. The variable resistance can be at a maximum in the absence of an expansion device (140) and at less than maximum in the presence of an expansion device. The first intermediate voltage and a second intermediate voltage (145) can be introduced to a comparator (150). The comparator can provide an output signal (170) when the first intermediate voltage exceeds the second intermediate voltage. The comparator output signal can be used to confirm the power supply capacity to power an external device (180) and to enable one or more external device functions.

Abstract: A computing system is associated with power consumption based on Power over Ethernet (PoE). Power consumption is compared to a threshold, and a signal is asserted that power consumption is to be limited based on the comparison to the threshold.

Abstract: Electronic circuits and methods are provided for conserving power within computers and other apparatus. A logic circuit performs a logical operation on a plurality of variables thus deriving a corresponding output. The output is used to drive and maintain an open or closed state of an electronic switch, accordingly. The electronic switch is disposed between a source of electrical energy and a system power buss of a computer. The computer can assume very low power, full power and other respective operating modes in accordance with the present state of the electronic switch.

Abstract: A first resistance (125) within a power supply (110) can be connected to a power supply output (120). A variable resistance (130) can be serially coupled with the first resistance, thereby providing a first intermediate voltage at a point (115) disposed between the first resistance and the variable resistance. The variable resistance can be at a maximum in the absence of an expansion device (140) and at less than maximum in the presence of an expansion device. The first intermediate voltage and a second intermediate voltage (145) can be introduced to a comparator (150). The comparator can provide an output signal (170) when the first intermediate voltage exceeds the second intermediate voltage. The comparator output signal can be used to confirm the power supply capacity to power an external device (180) and to enable one or more external device functions.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion across on a plurality of memory cartridges each containing a plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). Each memory cartridge includes an independent memory controller and a corresponding control mechanism in the host/data controller to interpret the independent transitioning of each memory cartridge between various states, including a redundant-ready and a powerdown state to facilitate “hot-plug” capabilities utilizing the removable memory cartridges. Fault information may be passed between the individual memory controllers and the host/data controller to facilitate expedient fault isolation.

Abstract: A system and technique for correcting data errors in a memory device. More specifically, data errors in a memory device are corrected by scrubbing the corrupted memory device. Generally, a host controller delivers a READ command to a memory controller. The memory controller receives the request and retrieves the data from a memory sub-system. The data is delivered to the host controller. If an error is detected, a scrub command is induced through the memory controller to rewrite the corrected data through the memory sub-system. Once a scrub command is induced, an arbiter schedules the scrub in the queue. Because a significant amount of time can occur before initial read in the scrub write back to the memory, an additional controller may be used to compare all subsequent READ and WRITE commands to those scrubs scheduled in the queue.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The system supports DIMMs having X4 and X8 configurations. The system also transitions between various states, including a redundant state and a non-redundant state, to facilitate “hot-plug” capabilities utilizing its removable memory cartridges.

Abstract: A system and technique for detecting data errors in a memory device. More specifically, data errors in a memory device are detected by initiating an internal READ command or verify operation from a set of logic which is internal to the memory system in which the memory devices reside. Rather than relying on a READ command to be issued from an external device, via a host controller, the verify logic initiates verify routine in response to an event such as an operator instruction, hot-plug operation, or a periodic schedule. By implementing the verify operation, the system does not rely on external READ commands to verify data integrity. The verify routine may rely on typical ECC error logging mechanisms and may be used in a RAID memory architecture. Further, the verify routine may be used in conjunction with other error logging and correction logic, as well as scrubbing logic.

Abstract: A power control feature in a computer system. The power control feature includes a host having a motherboard with a first connector that allows motherboard signals to be shared internal to the host. The motherboard also has a second connector separate from the first connector that supports communications with the host. An extension transmitter card is included within the host and is electrically coupled to the motherboard of the host via at least the first connector and the second connector. The extension transmitter card includes an extension transmitter device that has circuitry configured to recognize specific programmable key code combinations from a keyboard. One function of the key code combinations is to indicate powering on or off the host. An extension receiver is also included in the computer system and is connected to a plurality of user interface devices including the keyboard. The extension receiver is extensibly connected to the extension transmitter card.

Abstract: A computer interface extension configuration that includes a host having a motherboard, an extension transmitter card, and an extension receiver. The motherboard includes a first connector that allows motherboard signals to be shared internal to the host, and a second connector separate from the first connector that supports communications with the host. The extension transmitter card is positioned within the host and is electrically connected to the motherboard of the host via at least the first connector and the second connector. The extension transmitter card includes an extension transmitter device having endpoint circuitry that provides the host with information for enumeration, manageability, and security. The extension receiver is connected to a plurality of user interface devices and is extensibly connected to the extension transmitter card.

Abstract: A computer interface extension configuration that includes a host, an extension transmitter, an extension receiver, and user interface devices such as a keyboard, mouse, and video devices. The host has a motherboard with a first connector that allows motherboard signals to be shared internal to the host. The motherboard also has a second connector separate from the first connector that supports communications with the host. An extension transmitter card is inserted within the host and is connected to the motherboard of the host via at least the first connector. The extension transmitter card has an extension controller or transmitter core that adapts to the functionality distribution of the extension transmitter. An extension receiver is included in the computer interface extension configuration as an interface to a plurality of user interface devices.

Abstract: A computer interface extension configuration that includes a host having a motherboard, an extension transmitter card, and an extension receiver. The motherboard includes a first connector that allows motherboard signals to be shared internal to the host, and a second connector separate from the first connector that supports communications with the host. The extension transmitter card is positioned within the host and is electrically connected to the motherboard of the host via at least the first connector and the second connector. The extension transmitter card has a graphics controller that interfaces with the second connector independent from communications that occur on the first connector. The extension receiver is connected to a plurality of user interface devices and extensibly connected to the extension transmitter card.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion across on a plurality of memory cartridges each containing a plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). Each memory cartridge includes an independent memory controller and a corresponding control mechanism in the host/data controller to interpret the independent transitioning of each memory cartridge between various states, including a redundant-ready and a powerdown state to facilitate “hot-plug” capabilities utilizing the removable memory cartridges. Fault information may be passed between the individual memory controllers and the host/data controller to facilitate expedient fault isolation.