Patents by Inventor Patrick La Fratta
Patrick La Fratta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972152Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.Type: GrantFiled: January 11, 2023Date of Patent: April 30, 2024Inventors: Patrick A. La Fratta, Robert Walker
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Patent number: 11928055Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.Type: GrantFiled: October 27, 2022Date of Patent: March 12, 2024Assignee: Micron Technology, Inc.Inventors: Patrick A. La Fratta, Robert Walker, Chandrasekhar Nagarajan
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Publication number: 20240078030Abstract: Apparatuses and methods related to port arbitration of a memory system are described. A memory system can receive a first number of transactions and a second transaction from a first traffic stream and a third number of transactions and a fourth transaction from a second traffic stream. The memory system can process the first number of transactions at least partially concurrently with the third number of transactions. Responsive to a total quantity of transactions of the first number of transactions and the second transaction being at least a threshold quantity of transactions, the second transaction can be processed by the memory system and, subsequent to processing the second transaction, the fourth transaction can be processed by the memory system.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Inventors: Patrick A. La Fratta, Shashank Adavally, Jeffrey L. Scott, Robert M. Walker
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Patent number: 11853578Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a component, such as a controller, for facilitating a transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may receive an indication of the data migration operation from a host device and may initiate a transfer of data between the first and second memory devices. The controller may include one or more buffers to store data being transferred between the first and second memory devices. In some cases, the transfer of data between the first and second memory devices may occur within the memory system and without being transferred through the host device.Type: GrantFiled: October 27, 2021Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
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Patent number: 11782626Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a data migration component, such as a driver, for facilitating the transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may indicate the data migration operation to a second component (e.g., a controller) of the memory system. The second component may initiate the transfer of data between the first memory device and the second memory device based on the receiving the indication of the data migration operation. In some cases, the transfer of data between the first memory device and the second memory device may occur within the memory system without being transferred through a host device.Type: GrantFiled: October 26, 2021Date of Patent: October 10, 2023Assignee: Micron Technology, Inc.Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
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Patent number: 11709613Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.Type: GrantFiled: January 20, 2022Date of Patent: July 25, 2023Assignee: Micron Technology, Inc.Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
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Patent number: 11698756Abstract: Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.Type: GrantFiled: February 28, 2022Date of Patent: July 11, 2023Assignee: Micron Technology, Inc.Inventors: Dhawal Bavishi, Patrick A. La Fratta
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Patent number: 11625197Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.Type: GrantFiled: October 11, 2021Date of Patent: April 11, 2023Assignee: Micron Technology, Inc.Inventors: Patrick A. La Fratta, Robert Walker
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Publication number: 20230060826Abstract: A system includes a processing device that determines whether a memory bank is active and adds an activate command for a row of the memory bank accessed by an oldest command for the memory bank to a command scheduler in response to determining the memory bank is not active. The processing device determines whether the row of the memory bank has a corresponding row command in response to determining the memory bank is active. The processing device determines whether a close page mode is enabled or an open row timer has expired on the row and adds a precharge command to the command scheduler in response to determining the close page mode is enabled or the open row timer has expired. The processing device executes a command in the command scheduler based on a priority of commands included in the command scheduler.Type: ApplicationFiled: September 1, 2021Publication date: March 2, 2023Inventors: Patrick A. La Fratta, Jeffrey L. Scott, Laurent Isenegger, Robert M. Walker
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Patent number: 11593027Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.Type: GrantFiled: December 18, 2020Date of Patent: February 28, 2023Assignee: Micron Technology, Inc.Inventors: Patrick A. La Fratta, Robert M. Walker
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Patent number: 11586390Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.Type: GrantFiled: October 11, 2021Date of Patent: February 21, 2023Assignee: Micron Technology, Inc.Inventors: Patrick A. La Fratta, Robert Walker
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Publication number: 20230053291Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.Type: ApplicationFiled: October 27, 2022Publication date: February 16, 2023Inventors: Patrick A. La Fratta, Robert Walker, Chandrasekhar Nagarajan
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Patent number: 11567700Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.Type: GrantFiled: April 6, 2021Date of Patent: January 31, 2023Assignee: Micron Technology, Inc.Inventors: Patrick A. La Fratta, Robert Walker
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Patent number: 11543978Abstract: A method is described that includes receiving a plurality of streams of memory requests and each stream is associated with a source. The method further includes determining a bandwidth allocation for each stream, wherein each allocation represents a portion of a total bandwidth of a memory component managed by the subsystem and each allocation indicates a priority of a corresponding stream based on a corresponding source of each stream and assigning a set of credits to each stream based on the bandwidth allocations. The method also includes determining a memory command from a queue for issuance, wherein each memory command in the queue is associated with a stream and determining the memory command is based on the credits assigned to each stream such that commands associated with a stream with a higher number of credits is given priority for issuance over commands associated with a stream with a lower number.Type: GrantFiled: July 14, 2020Date of Patent: January 3, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Patrick A. La Fratta, Robert M. Walker
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Patent number: 11526306Abstract: Methods, systems, and apparatus for command scheduling in a memory subsystem according to a selected scheduling ordering are described. Scheduling orderings are determined for a set of commands, where a scheduling ordering identifies an order by which a memory subsystem controller is to issue each command in the set of commands to the memory device. Scores are calculated for the scheduling orderings. A score of the plurality of scores includes a measure of performance of execution of the set of commands according to the scheduling ordering. A scheduling ordering is selected from the scheduling orderings based on the scores, and a command is issued to the memory device according to the scheduling ordering.Type: GrantFiled: May 18, 2021Date of Patent: December 13, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Patrick A. La Fratta, Robert M. Walker
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Publication number: 20220374166Abstract: Methods, systems, and apparatus for command scheduling in a memory subsystem according to a selected scheduling ordering are described. Scheduling orderings are determined for a set of commands, where a scheduling ordering identifies an order by which a memory subsystem controller is to issue each command in the set of commands to the memory device. Scores are calculated for the scheduling orderings. A score of the plurality of scores includes a measure of performance of execution of the set of commands according to the scheduling ordering. A scheduling ordering is selected from the scheduling orderings based on the scores, and a command is issued to the memory device according to the scheduling ordering.Type: ApplicationFiled: May 18, 2021Publication date: November 24, 2022Inventors: Patrick A. LA FRATTA, Robert M. WALKER
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Patent number: 11507504Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.Type: GrantFiled: March 17, 2021Date of Patent: November 22, 2022Assignee: Micron Technology, Inc.Inventors: Patrick A. La Fratta, Robert Walker, Chandrasekhar Nagarajan
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Patent number: 11442648Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.Type: GrantFiled: August 17, 2020Date of Patent: September 13, 2022Assignee: Micron Technology, Inc.Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
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Publication number: 20220179590Abstract: Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Inventors: Dhawal Bavishi, Patrick A. La Fratta
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Publication number: 20220147262Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.Type: ApplicationFiled: January 20, 2022Publication date: May 12, 2022Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta