Patents by Inventor Patrick Larsson

Patrick Larsson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof
    Patent number: 7426247
    Abstract: A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes:(1) a central frequency synthesizer configured to provide both in-phase and quadrature-phase clock signals and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer. Each of the plurality of channel-specific receivers is configured to receive and deserialize a data signal and include a clock recovery circuit having a phase detector and a phase interpolator. The interpolator is configured to receive the clock signals from the central frequency synthesizer and couple the phase detector and the central frequency synthesizer.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: September 16, 2008
    Assignee: Agere Systems Inc.
    Inventors: Fuji Yang, Patrick Larsson, Jay O'Neill
  • MULTI-CHANNEL SERDES RECEIVER FOR CHIP-TO-CHIP AND BACKPLANE INTERCONNECTS AND METHOD OF OPERATION THEREOF
    Publication number: 20070092039
    Abstract: A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes:(1) a central frequency synthesizer configured to provide both in-phase and quadrature-phase clock signals and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer. Each of the plurality of channel-specific receivers is configured to receive and deserialize a data signal and include a clock recovery circuit having a phase detector and a phase interpolator. The interpolator is configured to receive the clock signals from the central frequency synthesizer and couple the phase detector and the central frequency synthesizer.
    Type: Application
    Filed: November 17, 2006
    Publication date: April 26, 2007
    Applicant: Agere Systems Incorporated
    Inventors: Fuji Yang, Patrick Larsson, Jay O'Neill
  • Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof
    Patent number: 7158587
    Abstract: A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes: (1) a PLL-based central frequency synthesizer and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer, each of the plurality including a clock recovery system having a phase detector and a phase interpolator, the clock recovery system coupling the phase detector and the central frequency synthesizer.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: January 2, 2007
    Assignee: Agere Systems Inc.
    Inventors: Fuji Yang, Patrick Larsson, Jay O'Neill
  • Four quadrant analog mixer-based delay-locked loop for clock and data recovery
    Patent number: 6586977
    Abstract: A delay-locked loop (DLL) and a method of performing clock and data recovery. In one embodiment, the DLL includes: (1) a phase detector that generates a phase difference signal based on a phase comparison between a data signal and a mixer output signal of the DLL and (2) a quadrant controller, coupled to the phase detector, that generates first and second voltage control signals based on the phase difference signal and first and second voltage control signals of the DLL.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: July 1, 2003
    Assignee: Agere Systems Inc.
    Inventors: Fuji Yang, Patrick Larsson
  • Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof
    Publication number: 20030053565
    Abstract: A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes: (1) a PLL-based central frequency synthesizer and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer, each of the plurality including a clock recovery system having a phase detector and a phase interpolator, the clock recovery system coupling the phase detector and the central frequency synthesizer.
    Type: Application
    Filed: September 18, 2001
    Publication date: March 20, 2003
    Inventors: Fuji Yang, Patrick Larsson, Jay O'Neill
  • Four quadrant analog mixer-based delay-locked loop for clock and data recovery
    Publication number: 20020097073
    Abstract: A delay-locked loop (DLL) and a method of performing clock and data recovery. In one embodiment, the DLL includes: (1) a phase detector that generates a phase difference signal based on a phase comparison between a data signal and a mixer output signal of the DLL and (2) a quadrant controller, coupled to the phase detector, that generates first and second voltage control signals based on the phase difference signal and first and second voltage control signals of the DLL.
    Type: Application
    Filed: September 6, 2001
    Publication date: July 25, 2002
    Applicant: Agere Systems Inc.
    Inventors: Fuji Yang, Patrick Larsson