Abstract: A cryptographic integrated circuit including a programmable main processor for executing cryptographic functions, an internal memory, and a data transmission bus to which the main processor and the internal memory are electrically connected. The cryptographic integrated circuit also includes a programmable arithmetic coprocessor that has specific hardware arithmetic units each being designed to carry out a predetermined arithmetical operation. The programmable arithmetic coprocessor is separate from the main processor and is also electrically connected to the data transmission bus.

Abstract: This cryptographic integrated circuit 10 comprises a programmable main processor (12) for executing cryptographic functions, an internal memory (14), and a data transmission bus (16) to which the main processor (12) and the internal memory (14) are electrically connected. Moreover, it comprises a programmable arithmetic coprocessor (18) comprising specific hardware arithmetic units (30, 32, 34), each of these specific hardware arithmetic units being designed to carry out a predetermined arithmetical operation. This programmable arithmetic coprocessor (18) is separate from the main processor (12) and also electrically connected to the data transmission bus (16).

Abstract: The invention relates to a method for speeding up the time required to perform a Montgomery product calculation by applying the High-Radix Montgomery method on computing hardware. A loop of operations is performed consisting in repeating successive operations, i.e.: a first addition operation involving the addition of a value of one of several first products, designated ai·b and a value of one variable, designated u, according to a first relationship u:=u+ai·b; and a second addition operation involving the addition of a value of one of several second products, designated m·n, and a value of variable u according to a second relationship u:=u+m·n. At least the first and second addition operations are Carry-Save addition operations in order to speed up the time required to perform an addition.

Abstract: A module for secure management of digital data by encryption/decryption and/or signature/verification of signature which can be used for dedicated servers. The module is controlled by a microprocessor (?P1). A working memory (RAM) is associated with the microprocessor and is provided with a common interfacing module. Parallel-connected to this common interfacing module and forming the internal circuits of said module are a plurality of circuits for secure management of data received from or respectively transmitted to the common interfacing module. Each secure management circuit forming an automatic secure management device is equipped with a secure management input/output sub-module connected to the common interfacing module and a specific sub-module for encryption/decryption or respectively for calculation/verification of signature.

Abstract: An encryption circuit for simultaneously processing various encryption algorithms, the circuit being capable of being coupled with a host system hosted by a computing machine. The circuit comprises an input/output module responsible for the data exchanges between the host system and the circuit via a dedicated bus. An encryption module coupled with the input/output module is in charge of the encryption and decryption operations. Isolation means between the input/output module and the encryption module makes the sensitive information stored in the encryption module inaccessible to the host system and ensures the parallelism of the operations performed by the input/output module and the encryption module. The circuit is supported on a peripheral component interconnect card. The circuit is specifically adapted to provide “hardware” protection of computer servers or stations.

Abstract: An encryption circuit for simultaneously processing various encryption algorithms, the circuit being capable of being coupled with a host system hosted by a computing machine. The circuit comprises an input/output module responsible for the data exchanges between the host system and the circuit via a dedicated bus. An encryption module coupled with the input/output module is in charge of the encryption and decryption operations. Isolation means between the input/output module and the encryption module makes the sensitive information stored in the encryption module inaccessible to the host system and ensures the parallelism of the operations performed by the input/output module and the encryption module. The circuit is supported on a peripheral component interconnect card. The circuit is specifically adapted to provide “hardware” protection of computer servers or stations.

Abstract: The present invention concerns a cryptographic system (1) with a modular architecture. Memory modules (3, 3?, 3?) make it possible to store information concerning authentication keys, data and commands, including a secure memory module (3?) for containing the keys with integrity checking and an emergency erase function. Various types of algorithm modules (5, 5?, 5?) perform cryptographic functions of the cryptographic system by executing the commands stored in at least one memory module (3, 3?, 3?). External interface modules (4, 4?, 4?) are utilized that make it possible to produce the link between the cryptographic system (1) and external devices, through a standard or proprietary input/output bus. A control unit (6) is responsible for the supervision of the various algorithm modules and the management of the keys, and a central interconnect module (2) assures handling of secure exchanges between blocks.

Abstract: A high-speed random number generator (1) comprising a physical random number generator, having a data input, an output and a pseudo-random generator coupled to the output of the physical random generator. The pseudo-random generator has an input adapted to receive a germ delivered by the physical generator and deliver at an output a pseudo-random output signal. The physical generator comprises a logic circuit that includes at least a data input (D) and a clock input (CLK), the data input (D) receiving a first “high frequency” clock signal H1 and the clock input (CLK) receiving a second “low frequency” clock signal H2, with the “high frequency” signal H1 being sampled by the “low frequency” signal H2. The two clock signals H1 and H2 are of different frequencies respectively and issue from two different first (OSC1 and OSC2) operating asynchronously from one another and not adhering to the setup time of the logic circuit (10).

Abstract: The invention relates to a method for speeding up the time required to perform a Montgomery product calculation by applying the High-Radix Montgomery method on computing hardware. A loop of operations (72) is performed consisting in repeating successive operations, i.e.: a first addition operation (76) involving the addition of a value of one of several first products, designated <o>ai</o>.<o>b</o>, and a value of one variable, designated u, according to a first relationship u:=u+<o>ai</o>.<o>b</o>; and a second addition operation (80) involving the addition of a value of one of several second products, designated m.n, and a value of variable u according to a second relationship u:=u+m.n. At least the first and second addition operations are Carry-Save addition operations in order to speed up the time required to perform an addition.

Abstract: A module for secure management of digital data by encryption/decryption and/or signature/verification of signature which can be used for dedicated servers.

Abstract: Physical random number generator, characterized in that it comprises a logic circuit (10) comprising at least a data input (D) and a clock input (CLK), the data input (D) receiving a first clock signal and the clock input (CLK) receiving a second clock signal different from the first one; and in that the two clock signals of different frequencies are respectively issued by two different oscillators (OSC1 and OSC2) operating asynchronously from one another and not adhering to the setup time of the logic circuit (10), the output of the circuit (10) delivering a signal in an intermediate state between “0” and “1,” qualified as metastable and being constituted by a random number sequence.

Abstract: A controller (CTMI) for multiple transfer of data organized by a microprocessor (MPU) between a plurality of memories (SRAM, VRAM) and a computer bus (PSB), including a plurality of registers (REGI, REGO) programmed by the microprocessor for writing into them of information enabling the organization of the transfer over a first and a second channel. The controller includes a central bus (BC, BC1) connected to each of the registers; a first and a second channel controller, associated with the first and second channel, respectively; and an arbitration device connected on the one hand to the second interface and on the other to each of the channel controllers. The arbitration device allocates a given channel to the data routes going to the memories or the microprocessor. The channel controllers control, for each channel, the writing access of the microprocessor to the registers associated with that channel and the transfer of data to each of the memories.