Patents by Inventor Patrick Llorens

Patrick Llorens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS AND SYSTEMS FOR SINGLE-EVENT UPSET FAULT INJECTION TESTING
    Publication number: 20220214951
    Abstract: Fault injection testing for field programmable gate array (FPGA) devices including: interfacing with a FPGA device under test (DUT); imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT where the CRAM includes a plurality of CRAM bits, injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating; concurrently monitoring operations of the FPGA DUT and a reference FPGA device; comparing outputs of the FPGA DUT with outputs of the reference FPGA device during concurrent operations, and if there is a mismatch between the outputs of the FPGA DUT and the reference FPGA, determining that error events have occurred within the FPGA DUT; and storing the error events and CRAM location data associated with corresponding single event upsets in an error log.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 7, 2022
    Applicant: Raytheon Company
    Inventors: Patrick Fleming, Mustafa Amin, James Bynes, III, Patrick Llorens, Dale D. Kachuche, Brian Clebowicz, William Rowe, Alfredo Lara, Neal Pollack
  • Methods and systems for single-event upset fault injection testing
    Patent number: 11378622
    Abstract: Fault injection testing for field programmable gate array (FPGA) devices including: interfacing with a FPGA device under test (DUT); imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT where the CRAM includes a plurality of CRAM bits, injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating; concurrently monitoring operations of the FPGA DUT and a reference FPGA device; comparing outputs of the FPGA DUT with outputs of the reference FPGA device during concurrent operations, and if there is a mismatch between the outputs of the FPGA DUT and the reference FPGA, determining that error events have occurred within the FPGA DUT; and storing the error events and CRAM location data associated with corresponding single event upsets in an error log.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: July 5, 2022
    Assignee: Raytheon Company
    Inventors: Patrick Fleming, Mustafa Amin, James Bynes, III, Patrick Llorens, Dale D. Kachuche, Brian Clebowicz, William Rowe, Alfredo Lara, Neal Pollack