Abstract: Techniques for dead producer elimination are described. In an embodiment, an apparatus includes micro-operation (uop) fusion circuitry to analyze a line of uops to find a producer uop and a consumer uop meeting fusibility criteria and to morph the consumer uop into a fused uop, wherein the line of uops includes a number of uops corresponding to a maximum number of uops that can be allocated in a single cycle; dead producer elimination (DPE) circuitry to determine that DPE conditions are satisfied; and an arithmetic-logic unit to execute the fused uop without the producer uop having been executed.

Abstract: Techniques and mechanisms for communicating information between clusters of a processor. In an embodiment, a processor core comprises circuitry to identify a condition wherein a first micro-operation (uop) of a uop sequence is to produce a value of an operand, a second uop of the uop sequence is to use the value of the operand, and different respective clusters of processor resources are to execute the first uop and the second uop. Based on the condition, the processor core supplements a strand of uops with a cross-cluster communication uop, wherein the strand comprises one of the first uop or the second uop. In another embodiment, one of the clusters executes the cross-cluster communication uop to provide a value of the operand to another cluster via a cross-cluster network.

Abstract: Systems, methods, and apparatuses relating to execution and retirement of auto-prediction code regions. For example, one embodiment of a processor comprises: decode circuitry to decode sequences of instructions, including one or more branch instructions, into sequences of microoperations (uops); execution circuitry to execute the sequences of uops; a branch predictor circuit to predict whether the one or more branch instructions will be taken; auto-predication circuitry to selectively perform predication operations within an auto-predication region of uops associated with the one or more branch instructions; and uop insertion circuitry to insert a selection uop at an end of the auto-predication region, the selection uop to select between a first value stored in a first physical register and a second value stored in a second physical register based on whether the auto-predicated region is determined to be not taken or taken, respectively.

Abstract: An apparatus and method for efficiently processing denormals on a processor. For example, one embodiment of a processor comprises: a decoder to decode instructions of a program code sequence into mircooperations (uops); a control register to store one or more bits related to denormal processing; uop morphing circuitry to generate or select a first type of FP divide or square root uop when the one or more bits indicate no possibility of denormals and to generate or select a second type of FP divide or square root uop when the one or more bits indicate a possibility of denormals; and execution circuitry to execute the first type of FP divide or square root uop to generate a result or to execute the second type of FP divide or square root uop, handling any denormals in hardware, to generate the result.

Abstract: Techniques for per allocation cycle micro-operation fusion are described. In an embodiment, an apparatus includes micro-operation (uop) fusion circuitry and an arithmetic-logic unit (ALU). The uop fusion circuitry is to analyze a line of uops to find a producer uop and a consumer uop meeting fusibility criteria and to morph the consumer uop into a fused uop, wherein the line of uops includes a number of uops corresponding to maximum number of uops that can be allocated in a single cycle. The ALU is to execute the fused uop.

Abstract: A method, computer system, and a computer program product for identifying one or more item restrictions of a user. The present invention may include obtaining a plurality of item data from one or more ingested items associated with the user by utilizing a blockchain structure. The present invention may then include obtaining a plurality of symptom data associated with one or more symptoms of the user. Further, the present invention may also include predicting the one or more item restrictions associated with the user based on the obtained plurality of item data from the one or more ingested items and the obtained plurality of symptom data.

Abstract: Generally, an integrated circuit, an apparatus and a method for buffering analog information capture first analog information with a capture element and store at least portions of the analog information in a first passive variable resistance memory element coupled to the capture element and in a second passive variable resistance memory element. The portions of the analog information stored in the first passive variable resistance memory element and in the second passive variable resistance memory element may be the same or may be different.

Abstract: Generally, an integrated circuit, an apparatus and a method for buffering analog information capture first analog information with a capture element and store at least portions of the analog information in a first passive variable resistance memory element coupled to the capture element and in a second passive variable resistance memory element. The portions of the analog information stored in the first passive variable resistance memory element and in the second passive variable resistance memory element may be the same or may be different.