Patents by Inventor Patrick M. Flynn
Patrick M. Flynn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11882774Abstract: Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.Type: GrantFiled: September 7, 2021Date of Patent: January 23, 2024Assignee: Micron Technology, Inc.Inventors: Rajasekhar Venigalla, Patrick M. Flynn, Josiah Jebaraj Johnley Muthuraj, Efe Sinan Ege, Kevin Lee Baker, Tao Nguyen, Davis Weymann
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Patent number: 11864475Abstract: Methods, systems, and devices for a memory device with laterally formed memory cells are described. A material stack that includes a conductive layer between multiple dielectric layers may be formed, where the conductive layer and dielectric layers may form a channel in a sidewall of the material stack. The channel may be filled with one or more materials, where a first side of an outermost material of the one or more materials may be exposed. An opening may be formed in the material stack that exposes a second side of at least one material of the one or more materials. The opening may be used to replace a portion of the at least one material with a chalcogenide material where the electrode materials may be formed before replacing the portion of the at least one material with the chalcogenide material.Type: GrantFiled: May 27, 2021Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Thomas M. Graettinger, Lorenzo Fratin, Patrick M. Flynn, Enrico Varesi, Paolo Fantini
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Publication number: 20220384722Abstract: Methods, systems, and devices for a memory device with laterally formed memory cells are described. A material stack that includes a conductive layer between multiple dielectric layers may be formed, where the conductive layer and dielectric layers may form a channel in a sidewall of the material stack. The channel may be filled with one or more materials, where a first side of an outermost material of the one or more materials may be exposed. An opening may be formed in the material stack that exposes a second side of at least one material of the one or more materials. The opening may be used to replace a portion of the at least one material with a chalcogenide material where the electrode materials may be formed before replacing the portion of the at least one material with the chalcogenide material.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Inventors: Thomas M. Graettinger, Lorenzo Fratin, Patrick M. Flynn, Enrico Varesi, Paolo Fantini
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Publication number: 20220069216Abstract: Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.Type: ApplicationFiled: September 7, 2021Publication date: March 3, 2022Inventors: Rajasekhar Venigalla, Patrick M. Flynn, Josiah Jebaraj Johnley Muthuraj, Efe Sinan Ege, Kevin Lee Baker, Tao Nguyen, Davis Weymann
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Patent number: 11121317Abstract: Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.Type: GrantFiled: November 14, 2019Date of Patent: September 14, 2021Assignee: Micron Technology, Inc.Inventors: Rajasekhar Venigalla, Patrick M. Flynn, Josiah Jebaraj Johnley Muthuraj, Efe Sinan Ege, Kevin Lee Baker, Tao Nguyen, Davis Weymann
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Publication number: 20210151675Abstract: Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.Type: ApplicationFiled: November 14, 2019Publication date: May 20, 2021Inventors: Rajasekhar Venigalla, Patrick M. Flynn, Josiah Jebaraj Johnley Muthuraj, Efe Sinan Ege, Kevin Lee Baker, Tao Nguyen, Davis Weymann
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Publication number: 20150206761Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.Type: ApplicationFiled: April 1, 2015Publication date: July 23, 2015Inventors: Janos Fucsko, David H. Wells, Patrick M. Flynn, Whonchee Lee
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Patent number: 8969217Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.Type: GrantFiled: July 22, 2013Date of Patent: March 3, 2015Assignee: Micron Technology, Inc.Inventors: Janos Fucsko, Niraj B. Rana, Sandra Tagg, Robert J. Hanson, Gundu M. Sabde, Donald L. Yates, Patrick M. Flynn, Prashant Raghu, Kyle Grant
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Publication number: 20130334594Abstract: Some embodiments include a memory device and a method of forming the memory device. One such memory device includes a string of stacked memory cells. Each of the memory cells in the string includes a charge storage structure and a recessed control gate. The recessed control gate has a substantially smooth surface separated from the charge storage structure by dielectric material. One such method includes etching heavily boron doped polysilicon selective to oxide to form a recessed control gate having a surface with nubs. A smoothing solution is applied to the surface of the recessed control gate to smoothen the nubs. Additional apparatuses and methods are described.Type: ApplicationFiled: June 15, 2012Publication date: December 19, 2013Inventors: Jerome A. Imonigie, Patrick M. Flynn, Sandra L. Tagg, Prashant Raghu
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Publication number: 20130302995Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.Type: ApplicationFiled: July 22, 2013Publication date: November 14, 2013Applicant: Micron Technology, Inc.Inventors: Janos Fucsko, Niraj B. Rana, Sandra Tagg, Robert J. Hanson, Gundu M. Sabde, Donald L. Yates, Patrick M. Flynn, Prashant Raghu, Kyle Grant
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Patent number: 8492288Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.Type: GrantFiled: June 10, 2008Date of Patent: July 23, 2013Assignee: Micron Technology, Inc.Inventors: Janos Fucsko, Niraj B. Rana, Sandra Tagg, Robert J. Hanson, Gundu M. Sabde, Donald L. Yates, Patrick M. Flynn, Prashant Raghu, Kyle Grant
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Publication number: 20090305511Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.Type: ApplicationFiled: June 10, 2008Publication date: December 10, 2009Inventors: Janos Fucsko, Niraj B. Rana, Sandra Tagg, Robert J. Hanson, Gundu M. Sabde, Donald L. Yates, Patrick M. Flynn, Prashani Raghu, Kyle Grant
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Patent number: 6790786Abstract: The invention includes semiconductor processing methods, including methods of forming capacitors. In one implementation, a semiconductor processing method includes providing a semiconductor substrate comprising a layer comprising at least one metal in elemental or metal alloy form. The metal comprises an element selected from the group consisting of platinum, ruthenium, rhodium, palladium, iridium, and mixtures thereof. At least a portion of the layer is etched in a halogenide, ozone and H2O comprising ambient.Type: GrantFiled: March 5, 2002Date of Patent: September 14, 2004Assignee: Micron Technology, Inc.Inventors: Paul A. Morgan, Patrick M. Flynn, Janos Fucsko
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Publication number: 20030170961Abstract: The invention includes semiconductor processing methods, including methods of forming capacitors. In one implementation, a semiconductor processing method includes providing a semiconductor substrate comprising a layer comprising at least one metal in elemental or metal alloy form. The metal comprises an element selected from the group consisting of platinum, ruthenium, rhodium, palladium, iridium, and mixtures thereof. At least a portion of the layer is etched in a halogenide, ozone and H2O comprising ambient.Type: ApplicationFiled: March 5, 2002Publication date: September 11, 2003Inventors: Paul A. Morgan, Patrick M. Flynn, Janos Fucsko
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Patent number: 6436287Abstract: A fuel pump module including a fuel reservoir, a fuel pump communicating with the fuel reservoir and having a fuel outlet, and a fuel filter assembly movably coupled to the fuel reservoir to facilitate installation of the fuel pump module into a fuel tank. The fuel filter assembly communicates with the fuel outlet to filter fuel that has passed through the fuel pump. In one aspect of the invention, the fuel filter assembly is pivotally movable with respect to the reservoir. In another aspect of the invention, the fuel filter assembly is linearly movable with respect to the reservoir.Type: GrantFiled: December 20, 2000Date of Patent: August 20, 2002Assignee: Robert Bosch CorportionInventors: Rolf Fischerkeller, Paul Wickett, Patrick M. Flynn
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Publication number: 20020074270Abstract: A fuel pump module including a fuel reservoir, a fuel pump communicating with the fuel reservoir and having a fuel outlet, and a fuel filter assembly movably coupled to the fuel reservoir to facilitate installation of the fuel pump module into a fuel tank. The fuel filter assembly communicates with the fuel outlet to filter fuel that has passed through the fuel pump. In one aspect of the invention, the fuel filter assembly is pivotally movable with respect to the reservoir. In another aspect of the invention, the fuel filter assembly is linearly movable with respect to the reservoir.Type: ApplicationFiled: December 20, 2000Publication date: June 20, 2002Inventors: Rolf Fischerkeller, Paul Wickett, Patrick M. Flynn