Abstract: An apparatus is provided that is implemented to enable multiple tests of different types, such as a direct current (DC) test and/or a radio frequency (RF) test of a semiconductor device. The apparatus includes a microelectromechanical systems (MEMS) switch block coupled between the semiconductor device and automatic testing equipment (ATE). The apparatus is configured to enable/disable a DC path or an RF path to switch between a DC test and an RF test without reconfiguring the connections between the semiconductor device and the ATE. The DC path is used to perform a DC contact test for one or more pins of the semiconductor device. The RF path is used to perform an RF test for the semiconductor device.

Abstract: An apparatus is provided that is implemented to enable multiple tests of different types, such as a direct current (DC) test and/or a radio frequency (RF) test of a semiconductor device. The apparatus includes a microelectromechanical systems (MEMS) switch block coupled between the semiconductor device and automatic testing equipment (ATE). The apparatus is configured to enable/disable a DC path or an RF path to switch between a DC test and an RF test without reconfiguring the connections between the semiconductor device and the ATE. The DC path is used to perform a DC contact test for one or more pins of the semiconductor device. The RF path is used to perform an RF test for the semiconductor device.

Abstract: Impedance paths for integrated circuits having microelectromechanical systems (MEMS) switches that allow for electrical charge to bleed from circuit nodes to fixed electric potentials (e.g., ground) are described. Such paths are referred to herein as charge bleed circuits. The circuit nodes may be circuit locations where electrical charge may accumulate because there is no other path for the electrical charge to dissipate. In some embodiments, a charge bleed circuit includes a switchable device (e.g., a MEMS switch, a solid-state device switch, or a circuit including various solid-state device switches that, collectively, implement a device that can be switched on and off) that connects and disconnects the impedance path from a circuit node. This may allow the device to perform different types of measurements at desired performance levels.

Abstract: Micro-isolators exhibiting enhanced isolation breakdown voltage are described. The micro-isolators may include an electrically floating ring surrounding one of the isolator elements of the micro-isolator. The isolator elements may be capacitor plates or coils. The electrically floating ring surrounding one of the isolator elements may reduce the electric field at the outer edge of the isolator element, thereby enhancing the isolation breakdown voltage.

Abstract: Micro-scale devices, such as transformers and capacitors, having a floating conductive layer are disclosed. A floating conductive layer may be disposed in an insulator layer and can reduce a maximum electric field between a first planar conductor and a second planar conductor of a micro-scale passive device. Reduction of a maximum electric field between a first planar conductor and a second planar conductor can reduce undesirable effects on electrical components.

Abstract: Micro-isolators exhibiting enhanced isolation breakdown voltage are described. The micro-isolators may include an electrically floating ring surrounding one of the isolator elements of the micro-isolator. The isolator elements may be capacitor plates or coils. The electrically floating ring surrounding one of the isolator elements may reduce the electric field at the outer edge of the isolator element, thereby enhancing the isolation breakdown voltage.

Abstract: An apparatus is provided that is implemented to enable multiple tests of different types, such as a direct current (DC) test and/or a radio frequency (RF) test of a semiconductor device. The apparatus includes a microelectromechanical systems (MEMS) switch block coupled between the semiconductor device and automatic testing equipment (ATE). The apparatus is configured to enable/disable a DC path or an RF path to switch between a DC test and an RF test without reconfiguring the connections between the semiconductor device and the ATE. The DC path is used to perform a DC contact test for one or more pins of the semiconductor device. The RF path is used to perform an RF test for the semiconductor device.

Abstract: Micro-isolators exhibiting enhanced isolation breakdown voltage are described. The micro-isolators may include an electrically floating ring surrounding one of the isolator elements of the micro-isolator. The isolator elements may be capacitor plates or coils. The electrically floating ring surrounding one of the isolator elements may reduce the electric field at the outer edge of the isolator element, thereby enhancing the isolation breakdown voltage.

Abstract: Isolators having a back-to-back configuration for providing electrical isolation between two circuits are described, in which multiple isolators formed on a single monolithic substrate are connect in series to achieve a higher amount of electrical isolation for a single substrate than for one of the isolators alone. A pair of isolators in the back-to-back configuration have top and bottom isolator components where the top isolator components are connected together and electrically isolated from the underlying substrate, resulting in floating top isolator components. The back-to-back isolator may provide one or more communication channels for transfer of information and/or power between different circuits.

Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.

Abstract: Micro-isolators exhibiting enhanced isolation breakdown voltage are described. The micro-isolators may include an electrically floating ring surrounding one of the isolator elements of the micro-isolator. The isolator elements may be capacitor plates or coils. The electrically floating ring surrounding one of the isolator elements may reduce the electric field at the outer edge of the isolator element, thereby enhancing the isolation breakdown voltage.

Abstract: Micro-scale devices, such as transformers and capacitors, having a floating conductive layer are disclosed. A floating conductive layer may be disposed in an insulator layer and can reduce a maximum electric field between a first planar conductor and a second planar conductor of a micro-scale passive device. Reduction of a maximum electric field between a first planar conductor and a second planar conductor can reduce undesirable effects on electrical components.

Abstract: Isolators having a back-to-back configuration for providing electrical isolation between two circuits are described, in which multiple isolators formed on a single, monolithic substrate are connected in series to achieve a higher amount of electrical isolation for a single substrate than for isolators formed on separate substrates connected in series. Discrete dielectric regions positioned between isolator components forming an isolator provide electrical isolation between the isolator components as well as between the isolators formed on the substrate. The back-to-back isolator may provide one or more communication channels for transfer of information and/or power between different circuits.

Abstract: Isolators having a back-to-back configuration for providing electrical isolation between two circuits are described, in which multiple isolators formed on a single monolithic substrate are connect in series to achieve a higher amount of electrical isolation for a single substrate than for one of the isolators alone. A pair of isolators in the back-to-back configuration have top and bottom isolator components where the top isolator components are connected together and electrically isolated from the underlying substrate, resulting in floating top isolator components. The back-to-back isolator may provide one or more communication channels for transfer of information and/or power between different circuits.

Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.

Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.

Abstract: An embodiment of a thermoelectric device may include a plurality of thermoelectric cells disposed between first and second planes. Each of the thermoelectric cells may include a thermoelectric element formed from a thermoelectric material of a single semiconductor type, the thermoelectric element including a first end, a second end, and a portion extending from the first end to the second end, the portion extending from the first end to the second end including at least two surfaces that face each other; and at least one conductive element electrically connected to and extending away from the second end of the thermoelectric element toward the first end of the thermoelectric element of another thermoelectric cell. Each thermoelectric cell also may further include an insulating element disposed between the at least two surfaces of the thermoelectric element and between portions of the at least one conductive element.

Abstract: Isolators having a back-to-back configuration for providing electrical isolation between two circuits are described, in which multiple isolators formed on a single, monolithic substrate are connected in series to achieve a higher amount of electrical isolation for a single substrate than for isolators formed on separate substrates connected in series. Discrete dielectric regions positioned between isolator components forming an isolator provide electrical isolation between the isolator components as well as between the isolators formed on the substrate. The back-to-back isolator may provide one or more communication channels for transfer of information and/or power between different circuits.

Abstract: An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer that are connected in series while alternating between the p-type and the n-type thermoelectric elements. The integrated circuit may include first and second substrates each having formed thereon a plurality of thermoelectric legs of a respective type of thermoelectric material. The first and second thermoelectric substrates also may have respective conductors, each coupled to a base of an associated thermoelectric leg and forming a mounting pad for coupling to a thermoelectric leg of the counterpart substrate.

Abstract: A magnetic isolator is described. The magnetic isolator may comprise a top conductive coil, a bottom conductive coil, and a dielectric layer separating the top conductive coil from the bottom conductive coil. The top conductive coil may comprise an outermost portion having multiple segments. The segments may be configured to reduce the peak electric field in a region of the dielectric layer near the outer edge of the top conductive coil. The top conductive coil may comprise a first lateral segment, and a second lateral segment that is laterally offset with respect to the first lateral segment. The first lateral segment may be closer to the center of the top conductive coil than the second lateral segment, and may be closer to the bottom conductive coil than the second lateral segment. The magnetic isolator may be formed using microfabrication techniques.