Abstract: Semiconductor devices and systems with arsenic-doped sources and drains that include phosphorus-doped contact regions, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes an epitaxial structure and a conductive contact. The epitaxial structure includes silicon, arsenic, and phosphorus, where phosphorus is concentrated in a contact region of the epitaxial structure. The conductive contact is coupled to the contact region of the epitaxial structure, and the conductive contact includes metal.

Abstract: In one embodiment, a transistor includes a substrate, a buffer layer on the substrate a channel layer on the buffer layer, and one or more polarization layers on the channel layer. The one or more polarization layers include a group III-N material comprising a first group III constituent and a second group III constituent. The transistor further includes a plurality of p-type doped layers on the one or more polarization layers. Each of the plurality of p-type doped layers includes a first p-type dopant and the III-N material, wherein each successive layer of the first p-type doped layers has a lower proportion of the first group III constituent to the second group III constituent relative to a layer below it. The transistor also includes a p-type doped layer on the plurality of p-type doped layers comprising a second p-type dopant and a group III-N material.

Abstract: In one embodiment, a transistor includes a substrate, a buffer layer on the substrate a channel layer on the buffer layer, and one or more polarization layers on the channel layer. The one or more polarization layers include a group III-N material comprising a first group III constituent and a second group III constituent. The transistor further includes a plurality of p-type doped layers on the one or more polarization layers. Each of the plurality of p-type doped layers includes a first p-type dopant and the III-N material, wherein each successive layer of the first p-type doped layers has a lower proportion of the first group III constituent to the second group III constituent relative to a layer below it. The transistor also includes a p-type doped layer on the plurality of p-type doped layers comprising a second p-type dopant and a group III-N material.

Abstract: In one embodiment, a transistor is formed by a process comprising forming a buffer layer on a substrate, the buffer layer comprising a first group III-nitride (III-N) material (e.g., AlGaN), forming a channel layer on the buffer layer, the channel layer comprising a second III-N material (e.g., GaN), forming a polarization layer on the channel layer, the polarization layer comprising a third III-N material (e.g., AlGaN), flowing a p-type dopant precursor compound (e.g., Cp2Mg) after forming the polarization layer, forming a p-type doped layer (e.g., p-GaN) on the polarization layer, the p-type doped layer comprising a p-type dopant (e.g., Mg) and a fourth III-N material (e.g., GaN), forming a source region adjacent one end of the channel layer, and forming a drain region adjacent another end of the channel layer.