Abstract: An enclosure kit for telecommunication cable, a method of making an enclosure kit for telecommunication cable, a method of storing a plurality of bases and pedestals and an enclosure assembly for telecommunication cable. By providing a tapered, generally how construction to both a ground-engaging base and an upward-extending pedestal, a telecommunication cable assembly may be formed, along with one or more locking features. Furthermore, by providing the tapered, generally how construction to both the base and the pedestal, groups of each may be nested in volumetrically-efficient packaging for shipping and storing. The size of the base may be made common to pedestals of numerous different sizes, thereby further simplifying packaging and shipping.

Abstract: An enclosure kit for telecommunication cable, a method of making an enclosure kit for telecommunication cable, a method of storing a plurality of bases and pedestals and an enclosure assembly for telecommunication cable. By providing a tapered, generally how construction to both a ground-engaging base and an upward-extending pedestal, a telecommunication cable assembly may be formed, along with one or more locking features. Furthermore, by providing the tapered, generally how construction to both the base and the pedestal, groups of each may be nested in volumetrically-efficient packaging for shipping and storing. The size of the base may be made common to pedestals of numerous different sizes, thereby further simplifying packaging and shipping.

Abstract: A system and method to perform an integrated circuit design involves selecting a net among a plurality of nets of the integrated circuit design as a victim net. Each net connects a pair of nodes of the integrated circuit design and each node represents a logic element of the integrated circuit design. The method also includes determining aggressor nets among the plurality of nets for the victim net and determining a corresponding weight value for each of the aggressor nets and, for each of the aggressor nets, multiplying the coupled noise originating from the aggressor net with the corresponding weight value to obtain a weighted coupled noise value. A cumulative coupled noise value is obtained for the victim net as a sum of the weighted coupled noise values associated with each of the aggressor nets. A result of the integrated circuit design is provided for fabrication into an integrated circuit.

Abstract: A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim circuit sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.

Abstract: A system and method to perform an integrated circuit design involves selecting a net among a plurality of nets of the integrated circuit design as a victim net. Each net connects a pair of nodes of the integrated circuit design and each node represents a logic element of the integrated circuit design. The method also includes determining aggressor nets among the plurality of nets for the victim net and determining a corresponding weight value for each of the aggressor nets and, for each of the aggressor nets, multiplying the coupled noise originating from the aggressor net with the corresponding weight value to obtain a weighted coupled noise value. A cumulative coupled noise value is obtained for the victim net as a sum of the weighted coupled noise values associated with each of the aggressor nets. A result of the integrated circuit design is provided for fabrication into an integrated circuit.

Abstract: A computer-implemented method for extracting a capacitance for a target wire of an integrated circuit includes receiving a design of the integrated circuit having a plurality of wiring layers and selecting a target wire to perform the capacitance extraction. The method further includes determining a first adjacent wiring layer and a second adjacent wiring layer and removing a first subset and a second subset of a plurality of non-adjacent wiring layers from the plurality of wiring layers. The method includes approximating a first plate to be used in the extraction based on the first subset of the plurality of non-adjacent wiring layers and approximating a second plate to be used in the extraction based on the second subset of the plurality of non-adjacent wiring layers and performing the extraction of the target wire based on the first and second adjacent wiring layers and the first and second plates.

Abstract: Coupled noise from at least one out-of-context aggressor net of an integrated circuit design is computed for an out-of-context victim net. The nets are out-of-context with respect to a hierarchical noise analysis of the integrated circuit design. At least one of the nets is a continuation of a path which extends to at least one in-context portion of the integrated circuit design. An aggressor signal timing window is derived for the at least one out-of-context aggressor net; a victim signal timing window is derived for the out-of-context victim net; and a timing window and noise analysis is completed with the aggressor signal timing window and the victim signal timing window. The aggressor window is derived as a function of required arrival time of the at least one out-of-context aggressor net and/or the victim window is derived as a function of required arrival time of the out-of-context victim net.

Abstract: A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC design, generating a blockage circuit section that represents a blockage aggressor circuit in the IC design, using the copied one or more victim circuit sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.

Abstract: A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.

Abstract: A system to design an integrated circuit and a method of fabricating an integrated circuit include performing a design change for a net among a plurality of nets of the integrated circuit. An extraction is performed for the net and includes re-computing values for a resistor-capacitor (RC) circuit representation of the net. Re-computed values resulting from the re-computing and a timestamp of the extraction are recorded. A capacitance value of a capacitor coupling the net with a neighboring net in the RC circuit representation of the neighboring net is changed to be the capacitance value of the capacitor coupling the net with the neighboring net that was re-computed for the RC circuit representation of the net. Timing and noise parameters are for the net and the neighboring net are updated to updated timing and noise parameters, and timing analysis is performed based on the updated timing and noise parameters.

Abstract: A system to design an integrated circuit and a method of fabricating an integrated circuit include performing a design change for a net among a plurality of nets of the integrated circuit. An extraction is performed for the net and includes re-computing values for a resistor-capacitor (RC) circuit representation of the net. Re-computed values resulting from the re-computing and a timestamp of the extraction are recorded. A capacitance value of a capacitor coupling the net with a neighboring net in the RC circuit representation of the neighboring net is changed to be the capacitance value of the capacitor coupling the net with the neighboring net that was re-computed for the RC circuit representation of the net. Timing and noise parameters are for the net and the neighboring net are updated to updated timing and noise parameters, and timing analysis is performed based on the updated timing and noise parameters.

Abstract: A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.

Abstract: A computer-implemented method for extracting a capacitance for a target wire of an integrated circuit includes receiving a design of the integrated circuit having a plurality of wiring layers and selecting a target wire to perform the capacitance extraction. The method further includes determining a first adjacent wiring layer and a second adjacent wiring layer and removing a first subset and a second subset of a plurality of non-adjacent wiring layers from the plurality of wiring layers. The method includes approximating a first plate to be used in the extraction based on the first subset of the plurality of non-adjacent wiring layers and approximating a second plate to be used in the extraction based on the second subset of the plurality of non-adjacent wiring layers and performing the extraction of the target wire based on the first and second adjacent wiring layers and the first and second plates.

Abstract: Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.

Abstract: The invention relates to an electromigration analysis method and a system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration. The method comprises the steps of providing at least one interconnect between a driver cell and at least one load cell; applying same extracted netlist data for noise and/or timing analysis and for electromigration analysis; modeling the driver cell by a train of trapezoidal voltage pulses transmitted from the driver cell to the one or more load cells through the at least one interconnect; extracting at least a slew rate of a driver voltage signal and/or timing information from a noise and/or timing analysis for the one or more nets; and comparing a locally measured current density in the at least one interconnect to an effective local maximum current density limit of the at least one interconnect.

Abstract: Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.

Abstract: Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

Abstract: An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.

Abstract: The invention relates to an electromigration analysis method and a system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration. The method comprises the steps of providing at least one interconnect between a driver cell and at least one load cell; applying same extracted netlist data for noise and/or timing analysis and for electromigration analysis; modeling the driver cell by a train of trapezoidal voltage pulses transmitted from the driver cell to the one or more load cells through the at least one interconnect; extracting at least a slew rate of a driver voltage signal (UD) and/or timing information from a noise and/or timing analysis for the one or more nets; and comparing a locally measured current density (if,rms,R32) in the at least one interconnect to an effective local maximum current density limit (irms,max) of the at least one interconnect.