Abstract: Integrated Doherty power amplifiers are provided herein. In certain implementations, a Doherty power amplifier includes a carrier amplification stage that generates a carrier signal, a peaking amplification stage that generates a peaking signal, and an antenna structure that combines the carrier signal and the peaking signal. The antenna structure radiates a transmit wave in which the carrier signal and the peaking signal are combined with a phase shift.

Abstract: Aspects of this disclosure relate to a radio frequency filter with two pass bands. The RF filter employs a first RF bandpass filter coupled to a common RF input and a common RF output. The RF filter further employs a second RF bandpass filter coupled to the common RF input and the common RF output. A first RF pass band of the first RF bandpass filter and a second RF pass band of the RF second bandpass filter are overlapping RF pass bands. Related methods and wireless communication devices are also disclosed.

Abstract: A differential circulator comprises first and second magnets, a ground plane, a first three-port junction conductor disposed between the first magnet and the ground plane, and a second three-port junction conductor disposed between the second magnet and the ground plane. The first three-port junction conductor and the second three-port junction conductor are in the same magnetic circuit including the first and second magnets to provide substantially same pass characteristics to radio frequency signals passing through the first three-port junction conductor and the second three-port junction conductor.

Abstract: Integrated Doherty power amplifiers are provided herein. In certain implementations, a Doherty power amplifier includes a carrier amplification stage that generates a carrier signal, a peaking amplification stage that generates a peaking signal, and an antenna structure that combines the carrier signal and the peaking signal. The antenna structure radiates a transmit wave in which the carrier signal and the peaking signal are combined with a phase shift.

Abstract: An antenna architecture can include a common node and a plurality of signal paths each having first and second ends, with the first end coupled to the common node, such that a common signal provided at the common node splits into respective signals in the signal paths. The antenna architecture can further include a phase shifter block implemented along each of at least some of the signal paths, with the phase shifter block including a phase shifting line to provide a phase shift for the signal passing through the respective signal path, such that the signals emerging from the signal paths are provided with incremental phase shifts. The antenna architecture can further include an antenna unit coupled to the second end of each signal path, such that the signals provided to the antenna units result in a transmitted signal being directed at a tilt angle with respect to the antenna units.

Abstract: Power amplifier having adaptive array size. In some embodiments, a power amplification system can include a power amplifier including a variable size array of transistors, and a monitoring system configured to monitor one or more conditions associated with the power amplifier. The power amplification system can further include a control system configured to obtain monitored information from the monitoring system, and based on the information, generate a control signal to adjust the size of the array of transistors.

Abstract: Power amplification system having forward and reverse coupling and digital predistortion compensation. In some embodiments, a power amplification system can include a power amplifier configured to receive an input signal and provide an amplified signal, and a coupler implemented relative to an output of the power amplifier and configured to measure forward power and reverse power at the output of the power amplifier. The power amplification system can further include a controller configured to receive information representative of the measured forward power and reverse power, and based on the information, generate a control signal for adjusting a parameter associated with the power amplifier.

Abstract: Amplification system having power amplifier memory correction and/or current collapse correction. In some embodiments, a power amplification system can include a power amplifier including an amplifying transistor configured to receive an input signal and provide an amplified signal, and a monitoring system configured to monitor one or more of a supply current for the amplifying transistor, an injection voltage point of the amplifying transistor, forward power at an output of the amplifying transistor, and temperature of the amplifying transistor. The power amplification system can further include a control system configured to obtain monitored information, and based on the information, generate a control signal for correcting either or both of a memory effect of the amplifying transistor and a current collapse effect of the amplifying transistor.

Abstract: Dynamic optimization of transistor array in power amplifier. In some embodiments, a power amplification system can include a power amplifier including an array of transistors, with the array configured to receive an input signal and provide an amplified signal. The power amplification system can further include a monitoring system including a plurality of sensing circuits implemented at respective locations of the array, and a control system configured to obtain sensed information from the plurality of sensing circuits, and based on the information, generate a pattern of one or more transistor properties over the array to allow operation of the array in a desired manner based on the pattern.

Abstract: A differential circulator comprises first and second magnets, a ground plane, a first three-port junction conductor disposed between the first magnet and the ground plane, and a second three-port junction conductor disposed between the second magnet and the ground plane. The first three-port junction conductor and the second three-port junction conductor are in the same magnetic circuit including the first and second magnets to provide substantially same pass characteristics to radio frequency signals passing through the first three-port junction conductor and the second three-port junction conductor.

Abstract: Systems and methods for differential antenna driving are provided. In one aspect, a front end system includes at least one power amplifier configured to receive a first transmit radio frequency signal from a baseband processor, amplify the first transmit radio frequency signal, and output the amplified first transmit radio frequency signal. The front end system further includes at least one balun configured to receive the amplified first transmit radio frequency signal. The at least one balun includes a positive output coupled to a first monopole of at least one antenna and a negative output coupled to a second monopole of the at least one antenna.

Abstract: Systems and methods for differential antenna driving are provided. In one aspect, a front end system includes at least one power amplifier configured to receive a first transmit radio frequency signal from a baseband processor, amplify the first transmit radio frequency signal, and output the amplified first transmit radio frequency signal. The front end system further includes at least one balun configured to receive the amplified first transmit radio frequency signal. The at least one balun includes a positive output coupled to a first monopole of at least one antenna and a negative output coupled to a second monopole of the at least one antenna.

Abstract: Integrated Doherty power amplifiers are provided herein. In certain implementations, a Doherty power amplifier includes a carrier amplification stage that generates a carrier signal, a peaking amplification stage that generates a peaking signal, and an antenna structure that combines the carrier signal and the peaking signal. The antenna structure radiates a transmit wave in which the carrier signal and the peaking signal are combined with a phase shift.

Abstract: Integrated Doherty power amplifiers are provided herein. In certain implementations, a Doherty power amplifier includes a carrier amplification stage that generates a carrier signal, a peaking amplification stage that generates a peaking signal, and an antenna structure that combines the carrier signal and the peaking signal. The antenna structure radiates a transmit wave in which the carrier signal and the peaking signal are combined with a phase shift.

Abstract: Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.

Abstract: Integrated Doherty power amplifiers are provided herein. In certain implementations, a Doherty power amplifier includes a carrier amplification stage that generates a carrier signal, a peaking amplification stage that generates a peaking signal, and an antenna structure that combines the carrier signal and the peaking signal. The antenna structure radiates a transmit wave in which the carrier signal and the peaking signal are combined with a phase shift.

Abstract: Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.

Abstract: Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.

Abstract: Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.