Abstract: An improved method is provided for managing workload on a multi-server computer system. In one embodiment, a subset of servers is selected according to an anticipated net workload. The remaining servers in the system may be powered off to conserve energy and prolong equipment life. Workload is dynamically apportioned among the subset of servers at selected intervals to more uniformly distribute the mean and variance of the workload among the subset of servers. More particularly, the mean and the variance for each of a plurality of workload units are equally weighed in determining a ranking of the workload units. The workload units may be ordered according to a mathematical combination of the mean and variance, such as the sum or product of mean and variance for each workload unit. The workload units are allocated among the subset of servers in according to rank, such as by assigning the workload units to the servers in a reverse round-robin fashion according to rank.

Abstract: An improved method is provided for managing workload on a multi-server computer system. In one embodiment, a subset of servers is selected according to an anticipated net workload. The remaining servers in the system may be powered off to conserve energy and prolong equipment life. Workload is dynamically apportioned among the subset of servers at selected intervals to more uniformly distribute the mean and variance of the workload among the subset of servers. More particularly, the mean and the variance for each of a plurality of workload units are equally weighed in determining a ranking of the workload units. The workload units may be ordered according to a mathematical combination of the mean and variance, such as the sum or product of mean and variance for each workload unit. The workload units are allocated among the subset of servers in according to rank, such as by assigning the workload units to the servers in a reverse round-robin fashion according to rank.

Abstract: An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank.

Abstract: Methods and arrangements to enhance a bus are disclosed. Embodiments may test bus segments, device interfaces, couplings between devices and device interfaces for bit errors. Several embodiments generate a test signal in response to coupling a device to a device interface, transmit the test signal on the bus, and generate an error signal when the bus signal at the device interface is different from the anticipated bus signal. The test signal may comprise one or more patterns of bits configured to identify one or more faults associated with a bus segment, a bus switch of the device interface to isolate the adapter card from the bus, and circuitry or buffers of the adapter card as plugged into the slot of the device interface. In many of these embodiments, a bus signal is determined at the bus-side and/or slot-side of the device interface.

Abstract: An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank.

Abstract: An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank.

Abstract: Methods and arrangements to enhance a bus are disclosed. Embodiments may test bus segments, device interfaces, couplings between devices and device interfaces for bit errors. Several embodiments generate a test signal in response to coupling a device to a device interface, transmit the test signal on the bus, and generate an error signal when the bus signal at the device interface is different from the anticipated bus signal. The test signal may comprise one or more patterns of bits configured to identify one or more faults associated with a bus segment, a bus switch of the device interface to isolate the adapter card from the bus, and circuitry or buffers of the adapter card as plugged into the slot of the device interface. In many of these embodiments, a bus signal is determined at the bus-side and/or slot-side of the device interface.

Abstract: A computer system with a shared-buffer memory includes a plurality of interconnected host systems. Each of the host systems includes system random access memory, with a portion of the system random access memory defined as shared-buffer memory. A system memory controller determines if the host has updated the shared-buffer memory, and if so, signals that the shared-buffer memory has been updated. This signal is accomplished by initiating a PCI Special Cycle which indicates the location and length in the shared-buffer of the update. A buffer control and interconnect device receives the signal from the system memory controller that the shared-buffer memory has been updated, reads the update from the shared-buffer memory, and exports the update. The exported update is received at the buffer control and interconnect device of each of the other host systems. The receiving buffer control and interconnect device writes the update to its shared-buffer memory.

Abstract: A method and system for hot-plugging a processor subsystem to a system bus of a data processing system while said data processing system is active, where the system bus comprises multiple positions for supporting hot-pluggable processor subsystems, where each processor subsystem includes a processor and associated voltage regulator module. Power is applied to a processor subsystem in response to an indication that the processor subsystem has been added to the system bus of the data processing system. Initialization routines are performed on the processor within the processor subsystem through a controller which transmits initialization data to the processor independent of the system bus, such that additional processor subsystems are integrated into the data processing system with minimal effect on any existing processors operating on the system bus.

Abstract: A method and arrangement is provided to support both fast Programmed Input/Output (PIO) and third party Direct Memory Access (DMA) data transfers between a system memory and Integrated Drive Electronics (IDE) drives. A DMA controller attached to an ISA bus supplies address, read and write signals in third party DMA data transfers. An IDE controller provides control signals to support the DMA data transfers. The IDE controller additionally provides address and control signals to support the PIO data transfers at local bus speeds. A local bus-ISA bridge is incorporated to support the system memory that resides on the local bus. An arbitration circuit arbitrates access to the ISA bus, and allows the IDE controller to seize the ISA bus for fast PIO data transfer.

Abstract: A bridge for interfacing buses in a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) control circuit programmable by programming signals to perform a DMA transfer. The DMA has registers for storing base addresses and registers for storing current addresses. The base addresses and the current addresses indicate destinations of transfer data in the DMA transfer. A power management device is coupled to the DMA control circuit and has logic for causing the computer system to enter a suspend mode. A base address register read circuit is coupled to the base address registers. Prior to entering the suspend mode, the base address register read circuit provides one of the base addresses to be read by a central processing unit (CPU) onto disk storage.