Abstract: An apparatus for implementing integrated circuit cooling during testing and image-based analysis thereof includes a lid configured to define a cavity surrounding an integrated circuit die, the die mounted to a module substrate. One or more fluid passages are defined within the lid, wherein the passages facilitate the flow of a cooling liquid through said cavity and over the integrated circuit die, and a transparent window is formed within the lid so as to facilitate viewing of the integrated circuit die.

Abstract: An apparatus for facilitating single die backside probing of semiconductor devices includes a chip holder configured for receiving a single integrated circuit die attached thereto, the chip holder maintained in flexible engagement in an X-Y orientation with respect to a lift plate. A lift ring is coupled to the lift plate, the lift ring configured to facilitate adjustment of the lift plate and the chip holder in a Z-direction.

Abstract: A technique is described for performing critical parameter analysis (CPA) of a semiconductor device (DUT) by combining the capabilities of conventional automated test equipment (ATE) with a focused optical beam scanning device such as a laser scanning microscope (LSM). The DUT is provided with a fixture such that it can be simultaneously scanned by the LSM or a similar device and exercised by the ATE. The ATE is used to determine pass/fail boundaries of operation of the DUT. Repeatable pass/fail limits (for timing, levels, etc.) are determined utilizing standard test patterns and methodologies. The ATE vector pattern(s) can then be programmed to “loop” the test under a known passing or failing state. When light energy from the LSM scanning beam sufficiently disturbs the DUT to produce a transition (i.e.