Abstract: Techniques to pre-warp an image based on an image warping map comprising a number of cells where each cell corresponds to a polynomial approximation for a number of corresponding pixels to be warped are described. An image warping map can be generated by partitioning a per pixel warping map into cells and approximating the pixel movements of each cell with a polynomial function.

Abstract: Techniques to pre-warp an image based on an image warping map comprising a number of cells where each cell corresponds to a polynomial approximation for a number of corresponding pixels to be warped are described. An image warping map can be generated by partitioning a per pixel warping map into cells and approximating the pixel movements of each cell with a polynomial function.

Abstract: A cache memory 2 includes error bits corresponding to each line of data. An error detecting circuit uses these error bits 12, 14, 16, 18 to detect if a soft error has occurred within the data of a cache line. If such an error has occurred, then the line may be refilled from the main memory or some other action taken, such as a write back or generation of a soft error abort signal.

Abstract: A direct memory access controller for controlling data transfer between a data source and a data destination comprising: a read/write port operable to receive data from said data source via a source bus and to output said received data to said data destination via a destination bus; wherein said direct memory access controller is operable in response to a predetermined number of clock pulses, to control said read/write port to output said received data said predetermined number of clock pulses after having received it. Also a direct memory access controller for controlling data transfer between a data source and a data destination comprising: a single read/write port comprising a read channel operable to receive data from said data source via a read path on a bus and a write channel operable to output said received data to said data destination via a write path on said bus, said read and write channel being operable to perform data reads and writes independently of each other.

Abstract: A data processor comprising: a control register operable to store a cache control value; and data accessing logic responsive to a data access instruction and to said cache control value to look for data to be accessed in a cache if said cache control value has a predetermined value and not to look for said data to be accessed in said cache if said cache control value does not have said predetermined value.