Abstract: A computer-implemented crime investigation system having a computer including a processor is operable to: receive and store one or more image data items, each of which shows one or more offenders in the process of committing an offence; authenticate a user belonging to a first access group; receive, via an application interface, case information from said user; attach portions of said case information, as indicated by said user using said application interface, to one or more of said image data items, as also indicated by said user using said application interface; search at least one of: said image data items or said case information based on search parameters; and return one or more search result image data items, having at least one of image data or attached case information which matches said search parameters, together with any of said case information attached to said search result image data items.

Abstract: A computer-implemented crime investigation system having a computer including a processor is operable to: receive and store one or more image data items, each of which shows one or more offenders in the process of committing an offence; authenticate a user belonging to a first access group; receive, via an application interface, case information from said user; attach portions of said case information, as indicated by said user using said application interface, to one or more of said image data items, as also indicated by said user using said application interface; search at least one of: said image data items or said case information based on search parameters; and return one or more search result image data items, having at least one of image data or attached case information which matches said search parameters, together with any of said case information attached to said search result image data items.

Abstract: A computer-implemented crime investigation system having a computer including a processor is operable to: receive and store one or more image data items, each of which shows one or more offenders in the process of committing an offence; authenticate a user belonging to a first access group; receive, via an application interface, case information from said user; attach portions of said case information, as indicated by said user using said application interface, to one or more of said image data items, as also indicated by said user using said application interface; search at least one of: said image data items or said case information based on search parameters; and return one or more search result image data items, having at least one of image data or attached case information which matches said search parameters, together with any of said case information attached to said search result image data items.

Abstract: A test method and apparatus for randomly testing logic structures. The method includes identifying and analyzing a functional behavior of a logic structure to be covered during the random testing, modifying the logic structure such that the logic structure behaves in a functional manner during random testing, and generating patterns to exercise the modified logic structure.

Abstract: A test method and apparatus for randomly testing logic structures. The method includes identifying and analyzing a functional behavior of a logic structure to be covered during the random testing, modifying the logic structure such that the logic structure behaves in a functional manner during random testing, and generating patterns to exercise the modified logic structure.

Abstract: An apparatus and method for allowing for dynamic wordline repair in a clock running system in addition to allowing for programmable fuse support of combined Array Built-In Self-Test (ABIST) and Logic Built-In Self-Test (LBIST) testing. The method makes use of programmable fuses which contain Level Sensitive Scan Design (LSSD) latches which also have a system port. The system port allows for simpler reading of the fuses as well as for the dynamic updates of the programmable fuses for wordline and other repairs.

Abstract: An apparatus and method for protecting a computer system from array reliability failures uses Array Built-In Self-Test logic along with code and hardware to delete cache lines or sets that are defective, identify corresponding fuse repair values, proactively call home if spare fuses are not available, schedule soft fuse repairs for the next system restart, schedule line deletes at the next restart, store delete and fuse repairs in a table (tagged with electronic serial id, timestamp of delete or ABIST fail event, address, and type of failure) and proactively call home if there were any missed deletes that were not logged. Fuse information can also be more permanently stored into hardware electronic fuses and/or EPROMs. During a restart, previous repairs are able to be applied to the machine so that ABIST will run successfully and previous deletes to be maintained with checking to allow some ABIST failures which are protected by the line deletes to pass.

Abstract: Methods and means of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.

Abstract: A method is disclosed for improving design criteria and importantly timing criteria following a metal-only engineering change. The method involves making initial logical changes involving new books (gate-level, filler-cell circuits, called ‘eco books’), running placement and routing with the new books, and timing the resulting logic. If there are timing violations, existing, non-filler books which are in close proximity are considered for swapping with the eco books. The book swaps are all done with wire connections only (i.e. the book placements are not affected). This way, critical paths and non-critical paths can be traded-off to achieve a faster design, even though books are not allowed to be moved. Some simple algorithms are discussed; however, there are many heuristic and analytic algorithms that can be applied in choosing swaps, based on the needs of the particular design.

Abstract: A method for deferred logging of machine data following an error or event in order to capture critical information for that error or event treats the data as persistent and it does not get logged until a disruption occurs to the system (e.g. system reset, restart, deactivation, or powered-down). This way, important debug data can be held in the hardware or software, without a need for complicated hardware and code for logging this debug data. Methods are also disclosed for setting a switch to indicate deferred logging is required, referencing the log data with the original event information, calling home with the debug data, resetting the deferred logging switch, setting the deferred logging switch manually, viewing whether the switch is already set, and supporting different kinds of switches.

Abstract: A method for minimizing the area of a binary orthogonality checker implemented in static CMOS circuits for minimizing the gate count and area needed for checker implementation. The method is adaptable to various libraries of logical gates to implement the circuit and the area for each gate in the library. The optimal mix of hierarchical levels and stages is determined such that the orthogonality checker achieves the minimized circuit area. An orthogonality checker is employed in a scalable selector system for controlling data transfers and routing in a data processing system to allow. Combining orthogonality checking with existing selector hierarchically allows for the maximum reuse of circuits, signals, and proximity; thus potentially reducing wiring as well. Multiple hierarchical checks are used in favor of one large. This structure is extended to multiple hierarchical levels and works with orthogonality checks of any size or implementation.

Abstract: The present invention provides a new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.