Abstract: A data processing system includes a shared random-access memory which is shared between a first and second asynchronous processor, wherein an access to the memory is clocked by a clock signal issuing from a first processor. A two-state selection signal is generated having a frequency equal to half the frequency of the clock signal. Access to the memory by the first processor to the memory is enabled when the selection signal is in a first state, and access to the memory by the second processor to the memory is enabled when the selection signal is in a second state. Thus, a memory is shared between two processors of different speeds, the clock signal therefore issuing from the faster processor.

Abstract: A processor has a local data bus to which an external read-only memory and a mailbox for exchanging data with a host computer may be connected. The processor is re-initialized, and a series of instructions is executed to write a program to be loaded into a program memory. The series of instructions includes an initial test of a state of the mailbox to determine whether data has been written to the input register of the mailbox from the host computer during the activation of the re-initialization signal. Depending on the results of this initial test, the program to be loaded is read either from the input register of the mailbox, or from the external read-only memory through the local data bus.