Patents by Inventor Patrick N. Conway

Patrick N. Conway has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10430343
    Abstract: A communication bypass mechanism accelerates cache-to-cache data transfers for communication traffic between caching agents that have separate last-level caches. A method includes bypassing a last-level cache of a first caching agent in response to a cache line having a modified state being evicted from a penultimate-level cache of the first caching agent and a communication attribute of a shadow tag entry associated with the cache line being set. The communication attribute indicates prior communication of the cache line with a second caching agent having a second last-level cache.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 1, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Patrick N. Conway
  • Patent number: 10387315
    Abstract: A memory access profiling and region migration technique makes allocation and replacement decisions for periodic migration of most frequently accessed regions of main memory to least frequently accessed regions of a region migration cache, in background operations. The technique improves performance in sparsely-used memory systems by migrating regions of main memory corresponding to the working footprint of main memory to the region migration cache. A method includes profiling a stream of memory accesses to generate an access frequency ranked list of address ranges of main memory and corresponding access frequencies based on memory addresses in the stream of memory accesses. The method includes periodically migrating to a region migration cache contents of a region of main memory selected based on the access frequency ranked list. The method includes storing a memory address range corresponding to the contents of the region migration cache in a tag map.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: August 20, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Patrick N. Conway
  • Publication number: 20180239708
    Abstract: A communication bypass mechanism accelerates cache-to-cache data transfers for communication traffic between caching agents that have separate last-level caches. A method includes bypassing a last-level cache of a first caching agent in response to a cache line having a modified state being evicted from a penultimate-level cache of the first caching agent and a communication attribute of a shadow tag entry associated with the cache line being set. The communication attribute indicates prior communication of the cache line with a second caching agent having a second last-level cache.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 23, 2018
    Inventor: Patrick N. Conway
  • Patent number: 9792210
    Abstract: A probe filter determines whether to issue a probe to at least one other processing node in response to a memory access request, and includes a region probe filter directory, a line probe filter directory, and a controller. The region probe filter directory identifies regions of memory for which at least one cache line may be cached in a data processing system and a state of each region, wherein a size of each region corresponds to a plurality of cache lines. The line probe filter directory identifies cache lines cached in the data processing system and a state of each cache line. The controller accesses at least one of the region probe filter directory and the line probe filter directory in response to a memory access request to determine whether to issue the probe, and does not issue any probe in response to a read-only request.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: October 17, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Patrick N. Conway
  • Publication number: 20170212845
    Abstract: A memory access profiling and region migration technique makes allocation and replacement decisions for periodic migration of most frequently accessed regions of main memory to least frequently accessed regions of a region migration cache, in background operations. The technique improves performance in sparsely-used memory systems by migrating regions of main memory corresponding to the working footprint of main memory to the region migration cache. A method includes profiling a stream of memory accesses to generate an access frequency ranked list of address ranges of main memory and corresponding access frequencies based on memory addresses in the stream of memory accesses. The method includes periodically migrating to a region migration cache contents of a region of main memory selected based on the access frequency ranked list. The method includes storing a memory address range corresponding to the contents of the region migration cache in a tag map.
    Type: Application
    Filed: April 11, 2016
    Publication date: July 27, 2017
    Inventor: Patrick N. Conway
  • Publication number: 20170177484
    Abstract: A probe filter determines whether to issue a probe to at least one other processing node in response to a memory access request, and includes a region probe filter directory, a line probe filter directory, and a controller. The region probe filter directory identifies regions of memory for which at least one cache line may be cached in a data processing system and a state of each region, wherein a size of each region corresponds to a plurality of cache lines. The line probe filter directory identifies cache lines cached in the data processing system and a state of each cache line. The controller accesses at least one of the region probe filter directory and the line probe filter directory in response to a memory access request to determine whether to issue the probe, and does not issue any probe in response to a read-only request.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Patrick N. Conway
  • Patent number: 8996816
    Abstract: A method and apparatus for selectively bypassing a cache in a processor of a computing device are disclosed. A mechanism to provide visibility to transactions on the core to a cache interface (e.g., an L3 cache interface) in a trace controller buffer (TCB) for debugging purposes, by causing selected transactions, which would otherwise be satisfied by the cache, to bypass the cache and be presented to the memory system where they may be logged in the TCB is described. In an embodiment of the invention, there is provided a method for providing processing core request visibility comprising bypassing a higher level cache in response to a processing core request, capturing the processing core request in a TCB, providing a mask to filter the processing core request, and returning a transaction response to a requesting processing core.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: March 31, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Greggory D. Donley, Benjamin Tsien, Vydhyanathan Kalyanasundharam, Patrick N. Conway, William A. Hughes
  • Publication number: 20120117330
    Abstract: A method and apparatus for a selectively bypassing a cache in a processor of a computing device are disclosed.
    Type: Application
    Filed: November 8, 2010
    Publication date: May 10, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Greggory D. Donley, Benjamin Tsien, Vydhyanathan Kalyanasundharam, Patrick N. Conway, William A. Hughes
  • Patent number: 8099557
    Abstract: In one embodiment, a system comprises a first processor, a main memory system, and a cache hierarchy coupled between the first processor and the main memory system. The cache hierarchy comprises at least a first cache. The first processor is configured to execute a first instruction, including forming an address responsive to one or more operands of the first instruction. The system is configured to push a first cache block that is hit by the first address in the first cache to a target location within the cache hierarchy or the main memory system, wherein the target location is unspecified in a definition of the first instruction within an instruction set architecture implemented by the first processor, and wherein the target location is implementation-dependent.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: January 17, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John D. McCalpin, Patrick N. Conway
  • Patent number: 7814286
    Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include initiating a first store operation to a cache data block stored in a first cache from a first processing node and initiating a first load operation to said cache data block from a second processing node subsequent to initiating said first store operation; and assigning a pairwise-shared directory state to a coherence directory entry corresponding to said cache data block in response to initiating said first load operation. The method may further include initiating a second store operation to said cache data block from said second processing node subsequent to initiating said first load operation; and assigning a migratory directory state to said coherence directory entry in response to initiating said second store operation, where the migratory directory state is distinct from a modified directory state.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: October 12, 2010
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Patrick N. Conway
  • Patent number: 7814285
    Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include initiating a first store operation to a cache data block stored in a first cache from a first processing node; assigning a modified cache state to said cache data block in response to initiating said first store operation. The method may further include initiating a first load operation to said cache data block from a second processing node; and assigning a pairwise-shared directory state to a coherence directory entry corresponding to said cache data block in response to initiating said first load operation, where the pairwise-shared directory state is distinct from a shared directory state.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: October 12, 2010
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Patrick N. Conway
  • Publication number: 20100146215
    Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include assigning an uncached directory state to a cache data block in response to evicting the cache data block. In another embodiment, the method may include assigning a remote directory state to a cache data block in response to evicting the cache data block and storing it in a remote cache. In a third embodiment, the method may include assigning a pairwise-shared directory state in response to a second processor node initiating a load operation to a cache data block in a modified cache state in a first processor node. In a fourth embodiment, the method may include assigning a migratory directory state in response to a processor node initiating a store operation to a cache data block in a pairwise-shared cache state.
    Type: Application
    Filed: February 18, 2010
    Publication date: June 10, 2010
    Inventor: Patrick N. Conway
  • Publication number: 20100146216
    Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include assigning an uncached directory state to a cache data block in response to evicting the cache data block. In another embodiment, the method may include assigning a remote directory state to a cache data block in response to evicting the cache data block and storing it in a remote cache. In a third embodiment, the method may include assigning a pairwise-shared directory state in response to a second processor node initiating a load operation to a cache data block in a modified cache state in a first processor node. In a fourth embodiment, the method may include assigning a migratory directory state in response to a processor node initiating a store operation to a cache data block in a pairwise-shared cache state.
    Type: Application
    Filed: February 18, 2010
    Publication date: June 10, 2010
    Inventor: Patrick N. Conway
  • Patent number: 7669018
    Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include initiating a first store operation to a cache data block stored in a first cache from a first processing node including the first cache and assigning a modified cache state to the cache data block in response to initiating the first store operation. The method may further include evicting the cache data block from the first cache subsequent to initiating the first store operation, storing the cache data block in a remote cache in response to the evicting, and assigning a remote directory state to a coherence directory entry corresponding to the cache data block in response to storing the cache data block in the remote cache, where the remote directory state is distinct from an invalid directory state.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: February 23, 2010
    Assignee: Globalfoundries Inc.
    Inventor: Patrick N. Conway
  • Patent number: 7669011
    Abstract: A processor includes a processor core coupled to an address translation storage structure. The address translation storage structure includes a plurality of entries, each corresponding to a memory page. Each entry also includes a physical address of a memory page, and a private page indication that indicates whether any other processors have an entry, in either a respective address translation storage structure or a respective cache memory, that maps to the memory page. The processor also includes a memory controller that may inhibit issuance of a probe message to other processors in response to receiving a write memory request to a given memory page. The write request includes a private page attribute that is associated with the private page indication, and indicates that no other processor has an entry, in either the respective address translation storage structure or the respective cache memory, that maps to the memory page.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: February 23, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Patrick N. Conway
  • Publication number: 20090216950
    Abstract: In one embodiment, a system comprises a first processor, a main memory system, and a cache hierarchy coupled between the first processor and the main memory system. The cache hierarchy comprises at least a first cache. The first processor is configured to execute a first instruction, including forming an address responsive to one or more operands of the first instruction. The system is configured to push a first cache block that is hit by the first address in the first cache to a target location within the cache hierarchy or the main memory system, wherein the target location is unspecified in a definition of the first instruction within an instruction set architecture implemented by the first processor, and wherein the target location is implementation-dependent.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 27, 2009
    Inventors: John D. McCalpin, Patrick N. Conway
  • Publication number: 20080215820
    Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include assigning an uncached directory state to a cache data block in response to evicting the cache data block. In another embodiment, the method may include assigning a remote directory state to a cache data block in response to evicting the cache data block and storing it in a remote cache. In a third embodiment, the method may include assigning a pairwise-shared directory state in response to a second processor node initiating a load operation to a cache data block in a modified cache state in a first processor node. In a fourth embodiment, the method may include assigning a migratory directory state in response to a processor node initiating a store operation to a cache data block in a pairwise-shared cache state.
    Type: Application
    Filed: May 12, 2008
    Publication date: September 4, 2008
    Inventor: Patrick N. Conway
  • Publication number: 20080155200
    Abstract: A processor includes a processor core coupled to an address translation storage structure. The address translation storage structure includes a plurality of entries, each corresponding to a memory page. Each entry also includes a physical address of a memory page, and a private page indication that indicates whether any other processors have an entry, in either a respective address translation storage structure or a respective cache memory, that maps to the memory page. The processor also includes a memory controller that may inhibit issuance of a probe message to other processors in response to receiving a write memory request to a given memory page. The write request includes a private page attribute that is associated with the private page indication, and indicates that no other processor has an entry, in either the respective address translation storage structure or the respective cache memory, that maps to the memory page.
    Type: Application
    Filed: December 21, 2006
    Publication date: June 26, 2008
    Inventor: Patrick N. Conway
  • Patent number: 7380001
    Abstract: A system and method for fault containment and error handling within a domain in a partitioned computer system includes a system manager having read and write access to a resource definition table. The system manager is adapted to quiesce the system when failure occurs within a domain, identify an allocated resource associated with the failed domain, identify a non-failed domain, and exit the quiesce mode for the non-failed domain, thereby containing a failure within the failed domain. The system manager further handles an error within the failed domain by deallocating a resource allocated to the failed domain so that the resource becomes available to non-failed domains.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: May 27, 2008
    Assignee: Fujitsu Limited
    Inventors: Kazunori Masuyama, Yasushi Umezawa, Jeremy J. Farrell, Sudheer Miryala, Takeshi Shimizu, Hitoshi Oi, Patrick N. Conway
  • Patent number: 7373466
    Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include assigning an uncached directory state to a cache data block in response to evicting the cache data block. In another embodiment, the method may include assigning a remote directory state to a cache data block in response to evicting the cache data block and storing it in a remote cache. In a third embodiment, the method may include assigning a pairwise-shared directory state in response to a second processor node initiating a load operation to a cache data block in a modified cache state in a first processor node. In a fourth embodiment, the method may include assigning a migratory directory state in response to a processor node initiating a store operation to a cache data block in a pairwise-shared cache state.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: May 13, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Patrick N. Conway