Abstract: A method of remapping allocated memory in a queue based switching element having first and second memory elements each allocated to a first port pair. An unallocated block of memory is identified in the first memory element as a candidate block, and an allocated block of memory is identified in the second memory element as a target block. Block information is copied from the target block to the candidate block, and the candidate block is maintained as unallocated. In response to a determination that read and write pointers are in a suitable position for a remapping operation, the candidate block is allocated and the target block is deallocated so that the second memory element becomes unallocated and available for reallocation to a second port pair.

Abstract: A method and apparatus for determining a set of common link rates for communication between two storage network elements in a storage network system. During the speed negotiation process, a controlling storage network element receives supported link rate information from a connected storage network element without providing any information in return. By not providing such information, although the speed negotiation process may not be completed, the controlling storage network element is still able to determine the supported link rates of the connected storage network element.

Abstract: A desired FIFO buffer fill level is continuously derived during mapping or demapping of plesiosynchronous data signals into synchronized data signals, or vice-versa. One of j predefined integer values Ii is repetitively consecutively produced during each consecutive one of j FIFO buffer write clock cycles, where i=1, . . . , j and where j and the integer values Ii are selected such that ? i = 1 j ? ? I i j closely approximates the number of bits read from the FIFO buffer per FIFO buffer write clock cycle. During each kth consecutive FIFO buffer write clock cycle, a Bits_Read value Ik+Ik-1 is produced where k=1, . . . , p; a Bits_Written value is produced; a Gap_Pattern value is derived by subtracting the Bits_Read value from the Bits_Written value; and, the Gap_Pattern is added to a predefined value representative a FIFO buffer center fill level to produce the desired FIFO buffer fill level.