Abstract: Process, cache memory, computer product and system for loading data associated with a requested address in a software cache. The process includes loading address tags associated with a set in a cache directory using a Single Instruction Multiple Data (SIMD) operation, determining a position of the requested address in the set using a SIMD comparison, and determining an actual data value associated with the position of the requested address in the set.

Abstract: A mechanism is provided for optimizing scalar code executed on a single instruction multiple data (SIMD) engine by aligning the slots of SIMD registers. With the mechanism, a compiler is provided that parses source code and, for each statement in the program, generates an expression tree. The compiler inspects all storage inputs to scalar operations in the expression tree to determine their alignment in the SIMD registers. This alignment is propagated up the expression tree from the leaves. When the alignments of two operands in the expression tree are the same, the resulting alignment is the shared value. When the alignments of two operands in the expression tree are different, one operand is shifted. For shifted operands, a shift operation is inserted in the expression tree. The executable code is then generated for the expression tree and shifts are inserted where indicated.

Abstract: A method for computing includes executing a program, including multiple cacheable lines of executable code, on a processor having a software-managed cache. A run-time cache management routine running on the processor is used to assemble a profile of inter-line jumps occurring in the software-managed cache while executing the program. Based on the profile, an optimized layout of the lines in the code is computed, and the lines of the program are re-ordered in accordance with the optimized layout while continuing to execute the program.

Abstract: Designing a computer program includes accessing invariant domain rules and displaying variable business rules. One or more business rules are selected in response to a user selection and are customized. The business rules are associated with a procedure, and the domain rules are associated with the procedure. A model representing the procedure is displayed, and a code corresponding to the procedure is generated to design a computer program.

Abstract: A compiler implemented software cache in which non-aliased explicitly fetched data are excluded are provided. With the mechanisms of the illustrative embodiments, a compiler uses a forward data flow analysis to prove that there is no alias between the cached data and explicitly fetched data. Explicitly fetched data that has no alias in the cached data are excluded from the software cache. Explicitly fetched data that has aliases in the cached data are allowed to be stored in the software cache. In this way, there is no runtime overhead to maintain the correctness of the two copies of data. Moreover, the number of lines of the software cache that must be protected from eviction is decreased. This leads to a decrease in the amount of computation cycles required by the cache miss handler when evicting cache lines during cache miss handling.

Abstract: A system and method for speculative assistance to a thread in a heterogeneous processing environment is provided. A first set of instructions is identified in a source code representation (e.g., a source code file) that is suitable for speculative execution. The identified set of instructions are analyzed to determine the processing requirements. Based on the analysis, a processor type is identified that will be used to execute the identified first set of instructions based. The processor type is selected from more than one processor types that are included in the heterogeneous processing environment. The heterogeneous processing environment includes more than one heterogeneous processing cores in a single silicon substrate. The various processing cores can utilize different instruction set architectures (ISAs). An object code representation is then generated for the identified first set of instructions with the object code representation being adapted to execute on the determined type of processor.

Abstract: A fixed-barrel, gas-operated firearm having its barrel concentrically mounted within a pressure tube enclosing substantially all of the moving parts of the firearm's action. A gas cup reciprocates under the influence of propellant gas pressure when the firearm is fired, driving slide members that link the pressure cup to the firearm's bolt rearward within the pressure tube, unlocking the breech, rotating and retracting the bolt, discharging the spent cartridge casing and then advancing the bolt to chamber a new cartridge.

Abstract: The present invention relates to support structures including truss assemblies and purlins, the truss assemblies including struts, wherein utilities such as pipes and cables can be contained within the purlins, and can pass through openings in the struts, to thereby be retained by the support structures so as to be hidden from view.

Abstract: Vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores is presented. In the framework presented herein, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler then inserts data reorganization operations to satisfy the actual alignment requirement of the hardware. Finally, the code generation algorithm generates SIMD codes based on the data reorganization graph, addressing realistic issues such as runtime alignments, unknown loop bounds, residue iteration counts, and multiple statements with arbitrary alignment combinations. Beyond generating a valid simdization, a preferred embodiment further improves the quality of the generated codes. Four stream-shift placement policies are disclosed, which minimize the number of data reorganization generated by the alignment handling.

Abstract: A “kill” intrinsic that may be used in programs for designating specific data objects as having been “killed” by a preceding action is provided. The concept of a data object being “killed” is that the compiler is informed that no operations (e.g., loads and stores) on that data object, or its aliases, can be moved across the point in the program flow where the data object is designated as having been “killed.” The “kill” intrinsic limits the reordering capability of an optimization scheduler of a compiler with regard to operations performed on “killed” data objects. The “kill” intrinsic may be used with direct memory access (DMA) operations. Data objects being DMA'ed from a local store of a processor may be “killed” through use of the “kill” intrinsic prior to submitting the DMA request. Data objects being DMA'ed to the local store of the processor may be “killed” after verifying the transfer completes.

Abstract: A system and method for dividing an application into a number of logical program partitions is presented. Each of these logical program partitions are stored in a logical program package along with a execution monitor. The execution monitor runs in one of the processing environments of a heterogeneous processing environment. The logical program partition includes sets of object code for executing on each of the types of processors included in the heterogeneous processing environment. The logical program partition includes instrumentation data used to evaluate the performance of a currently executing partition. The execution monitor compares the instrumentation data to the gathered profile data. If the execution monitor determines that the partition is performing poorly then the code for the other environment is retrieved from the logical program package and loaded and executed on the other environment.

Abstract: An approach for managing position independent code using a software framework is presented. A software framework provides the ability to cache multiple plug-in's which are loaded in a processor's local storage. A processor receives a command or data stream from another processor, which includes information corresponding to a particular plug-in. The processor uses the plug-in identifier to load the plug-in from shared memory into local memory before it is required in order to minimize latency. When the data stream requests the processor to use the plug-in, the processor retrieves a location offset corresponding to the plug-in and applies the plug-in to the data stream. A plug-in manager manages an entry point table that identifies memory locations corresponding to each plug-in and, therefore, plug-ins may be placed anywhere in a processor's local memory.

Abstract: A process for installing quoins to a building structure includes fabricating a plurality of quoins, each including two quoin panels angularly disposed relative to each other and connected along a common edge. A true edge column is attached to the building structure, the true edge column including two column panels angularly disposed relative to each other along a common column edge. The plurality of quoins are then attached in stacked relation over and to the true edge column. Each of the quoins may include an outer and an inner surface, wherein the inner surface comprises a right-angled recess adjacent to the common edge and along the two quoin panels. The true edge column may be cooperatively sized to fit within the right-angled recess. A plurality of pre-drilled apertures may be disposed about the right-angle recess for fastening the quoins to the true edge column and building structure.

Abstract: The APPARATUS, METHODS AND SYSTEMS FOR A LEAD EXCHANGE FACILITATING HUB (“HUB”) facilitates the generation, evaluation, and recording of information and activities related to property transactions and associated communications. In embodiments, the HUB may be configured to transaction and/or exchange of lead information, such as contact information, real estate site drives, market comparables, marketing ideas, and/or the like. The HUB may engender a tailored and efficient forum for coordinating transactions of lead information based on a centralized database of contacts and other lead information associated with and/or belonging to users. In one embodiment, users may submit lead requests comprising parameters and/or criteria based on which one or more queries may be performed on that database. Other users having leads matching the request may then be notified and may decide whether to share their lead information with the requesting user.

Abstract: The APPARATUSES, METHODS AND SYSTEMS FOR AN ACTIVITY TRACKING AND PROPERTY TRANSACTION FACILITATING HUB USER INTERFACE (“HUB”) facilitates the generation, evaluation, and recording of information and activities related to property transactions and associated communications. In one implementation, the HUB may allow for highly customizable mapping of spatiotemporal information in an integrated customer relationship management and real estate listing system; optimized scheduling of activities and/or appointments; efficient access to and economical display of contact information; dynamic sorting and filtering of searchable data; and/or the like.

Abstract: The APPARATUSES, METHODS AND SYSTEMS FOR AN INTELLIGENT INBOX COORDINATING HUB (“HUB”) facilitates the generation, evaluation, and recording of information and activities related to property transactions and associated communications. In embodiments, the HUB may be configured to effectuate intelligent inbox coordination, which may facilitate the processing of messages configured as email messages, XML data, HTTP POST message content, and/or the like for economical display and interaction. The HUB's intelligent inbox coordination features may allow for the distillation of large volumes of message data and/or content to highlight and/or direct users to the particular message and/or attachment containing data that is most interesting or relevant to them.

Abstract: The APPARATUSES, METHODS AND SYSTEMS FOR AN ACTIVITY TRACKING AND PROPERTY TRANSACTION FACILITATING HUB (“HUB”) facilitates the generation, evaluation, and recording of information and activities related to property transactions and associated communications. In one implementation, the HUB dynamically generates an interface based on a user role, allows quick and efficient viewing of information relevant to an actual or potential property transaction, and records user activities or interactions to allow future access to a given interface state or set of relationships defined by interface element values, such as they may pertain to the given property transaction, an associated counterparty or contact, and/or the like. In one implementation, the HUB may provide a bifurcated display to allow for side-by-side visualization of required and available property information, attributes, and/or the like.

Abstract: The APPARATUSES, METHODS AND SYSTEMS FOR A LEAD GENERATING HUB (“HUB”) facilitates the generation, evaluation, and recording of information and activities related to property transactions and associated communications. In embodiments, the HUB may be configured to identify leads for users based on user-entered information, user contacts, and/or the properties associated with a user and/or in which a user is interested. Leveraging connectivity between contract relationship management functionality, property listing service features, intelligent inbox coordination capabilities, and/or the like, the HUB may identify connections between user requirements and/or assets and opportunities to fulfill those requirements and/or to transact those assets.

Abstract: The present invention provides for a system for computer program functional partitioning for heterogeneous multi-processing systems. At least one system parameter of a computer system comprising one or more disparate processing nodes is identified. Computer program code comprising a program to be run on the computer system is received. A whole program representation is generated based on received computer program code. At least one single-entry-single-exit (SESE) region is identified based on the whole program representation. At least one node-specific SESE region is identified based on identified SESE regions and the at least one system parameter. Each node-specific SESE region is grouped into a node-specific subroutine. Each node-specific subroutine is compiled based on a specified node characteristic. The computer program code is modified based on the node-specific subroutines and the modified computer program code is compiled.

Abstract: The present invention provides for a system for computer program code size partitioning for multiple memory multi-processor systems. At least one system parameter of a computer system comprising one or more disparate processing nodes is identified. Computer program code comprising a program to be run on the computer system is received. A program representation based on received computer program code is generated. At least one single-entry-single-exit (SESE) region is identified based on the whole program representation. At least one SESE region of less than a certain size (store-size-specific) is identified based on identified SESE regions and the at least one system parameter. Each store-size-specific SESE region is grouped into a node-specific subroutine. The non node-specific parts of the computer program code are modified based on the partitioning into node-specific subroutines. The modified computer program code including each node-specific subroutine is compiled based on a specified node characteristic.