Abstract: A sorting assembly for sorting animals. The sorting assembly comprises a plurality of gates forming a visual barrier, each gate leading to a separate animals area. The gates are configured for movement between an opened position and a closed position. Only one gate may be in an opened position at a time. The gate in the opened position provides a contrast with gates in the closed position.

Abstract: A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

Abstract: A method, apparatus, and computer program product are disclosed for selectively prohibiting speculative conditional branch execution. A particular type of conditional branch instruction is selected. An indication is stored within each instruction that is the particular type of conditional branch instruction. A processor then fetches a first instruction from code that is to be executed. A determination is made regarding whether the first instruction includes the indication. In response to determining that the instruction includes the indication: speculative execution of the first instruction is prohibited, an actual location to which the first instruction will branch is resolved, and execution of the code is branched to the actual location. In response to determining that the instruction does not include the indication, the first instruction is speculatively executed.

Abstract: A method and apparatus for reforming a portion of a blow molded plastic container includes directing energy from a heater onto the portion of the container so as to heat the portion while leaving the remainder of the container relatively unheated. The heated portion of the container is then engaged by a reforming tool having an embossed or imprinted characteristic on a contact surface of the reforming tool so as to reform the portion of the container and form a three-dimensional feature thereon which is not reproducible without using the method and/or apparatus of the present invention. Alternatively, the heated portion of the container is engaged by a reforming tool having a transferable element on a contact surface of the reforming tool so as to reform the portion of the container and transfer the transferable element to the portion of the container.

Abstract: A method and apparatus for managing cache lines in a data processing system. A special purpose register is employed in which this register may be manipulated by user code and operating system code to set preferences, such as a level 2 cache management policy preference for an application thread. These preferences may be dynamically set and an arbitration mechanism is employed to best satisfy preferences of multiple threads with a single aggregate preference. Members are represented using a least recently used tree. The least recent used tree has a set of nodes forming a path to member cache lines in a hierarchical structure. A state of a selected node is selectively biased within the set of nodes in the least recently used tree. At least one node on a level below the selected node is eliminated from being selected in managing the cache lines. In this manner, members can be biased against or for selection as victims when replacing cache lines in a cache memory.

Abstract: A method of forming a gas tank filler neck includes configuring at least a portion of a one-piece seamless tubular member such that the seamless configuration induces a sufficient swirl to create a hollow passage for venting vapors from the gas tank during fuel filling. A method of forming the filler neck includes deep drawing a seamless funnel member having an elongated tubular body, forming a relatively large inlet at one end of the seamless funnel member, the inlet having a first axis, and forming a relatively small outlet at the opposite end of the seamless funnel member, the inlet having a second axis axially offset from said first axis.

Abstract: A method and apparatus for mapping some software prefetch instructions in a microprocessor system to a modified set of hardware prefetch instructions and executing the software prefetch by invoking the corresponding modified hardware prefetch instruction. For common software prefetch access patterns, by mapping the software prefetches to hardware, improved prefetching can be achieved without the need for additional hardware.

Abstract: A method and apparatus for managing cache lines in a data processing system. A special purpose register is employed in which this register may be manipulated by user code and operating system code to set preferences, such as a level 2 cache management policy preference for an application thread. These preferences may be dynamically set and an arbitration mechanism is employed to best satisfy preferences of multiple threads with a single aggregate preference. Members are represented using a least recently used tree. The least recent used tree has a set of nodes forming a path to member cache lines in a hierarchical structure. A state of a selected node is selectively biased within the set of nodes in the least recently used tree. At least one node on a level below the selected node is eliminated from being selected in managing the cache lines. In this manner, members can be biased against or for selection as victims when replacing cache lines in a cache memory.

Abstract: A method and apparatus for mapping some software prefetch instructions in a microprocessor system to a modified set of hardware prefetch instructions and executing the software prefetch by invoking the corresponding modified hardware prefetch instruction. For common software prefetch access patterns, by mapping the software prefetches to hardware, improved prefetching can be achieved without the need for additional hardware.

Abstract: A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction is used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine. The instruction also limits the amount of data to be prefetched.

Abstract: A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor.

Abstract: A cache memory having a mechanism for managing cache lines replacement is disclosed. The cache memory comprises multiple cache lines partitioned into a first group and a second group. The number of cache lines in the second group is preferably larger than the number of cache lines in the first group. A replacement logic block selectively chooses a cache line from one of the two groups of cache lines for replacement during an allocation cycle.

Abstract: A data processing system and method for prefetching data in a multi-level code subsystem. The data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache, and a third level cache and a system memory. Prefetching of cache lines is concurrently performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches are performed over a private or dedicated prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction or hint may be used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine.

Abstract: A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. The prefetch request may include a signal notifying the third level cache to also prefetch.

Abstract: A mains interface module is disclosed for a screened enclosure containing electronic equipment. A mains interface module for a screened enclosure containing electronic equipment has a screened casing having a weather proof mains inlet connector, one or more mains outlets and contains EMI filters operative to protect the outlet(s) from interference from a mains supply when connected to the inlet connector. The screening prevents radiation of interference within the enclosure. The weatherproof mains inlet allows the equipment to be used and installed outside. The EMI filters prevent interference from being conducted through the outlets.

Abstract: A system for performing molecular biological diagnosis, analysis and multistep and multiplex reactions utilizes a selfaddressable, selfassembling microelectronic system for actively carrying out controlled reactions in microscopic formats. Preferably, a fluidic system flow a sample across an active area of the biochip, increasing diagnostic efficiency. Preferably, the fluidic system includes aflow cell having a window. Pulsed activation of the electrodes of the biochip are advantageously employed with the fluidic system, permitting more complete sampling of the materials within the biological sample. An improved detection system utilizes a preferably coaxially oriented excitation fiber, such as a fiber optic, disposed within a light guide, such as a liquid light guide. In this way, small geometry systems may be fluorescently imaged. A highly automated DNA diagnostic system results.

Abstract: Integration of vehicle speed and engine control functions in an automotive vehicle internal combustion engine controller compensates for mechanical lash between a cruise control actuator and an engine intake air valve without sacrificing control responsiveness through a parallel control approach, and improves overall control stability and controllability in the absence of mechanical lash through a selective control approach established to provide for smooth transitions between control modes. Improvement in the integration of deceleration fuel cutoff control with cruise control operates to prevent torque disturbances caused by control transitions in sensitive engine operating regions.

Abstract: An amorphous silicon electrographic writing head assembly which reduces the voltage drift in the high voltage driving transistor. The writing head including a substrate having a first surface and a second surface, the first surface having thin film elements fabricated thereon, the first surface having a first region, a second region, and a third region, the first region including an array of writing electrodes, the second region including an array of high voltage transistors, and the third region including interconnecting circuitry for connecting the thin film elements to a connector. The head also includes a first cover glass fixed to the first surface of the array covering the first region and a second cover glass fixed to the first surface of the array covering the third region.

Abstract: An integrated thin film electrographic writing head. The writing head has integrated therein a plurality of marking electrodes or nibs arranged in a linear array for writing onto a medium, and a plurality of high voltage driving circuits for driving the nibs. The write head also includes a plurality of latches each connected to the high voltage driving circuits, a plurality of memory cells each connected to the latches, a plurality of buffers, each buffer supplying a select line to the plurality of memory cells, and a plurality of selection elements, supplying a selection signal to each of the buffers to drive a segment of memory cells. The integrated memory means and latching means allow for simultaneous latching and writing of an entire scanline of data.

Abstract: An improved electrographic writing head having electrode nibs for forming discrete electrostatic charges on a recording medium moved in a plane in contact with the nib ends in the head wherein the improvement comprises the employment of an impedance formed in the electrode nibs at or in proximity to the nib ends to reduce the intercoupling capacitance effect between adjacently disposed nibs to prevent flaring from occurring on the deposition of charge from the nib ends. The impedance is in the range of several megohms, such as, 50-1000 megohms.