Patents by Inventor Patrick O. Flynn

Patrick O. Flynn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11809570
    Abstract: A method and apparatus for analyzing side-channel security vulnerabilities in a digital device. A first time sequence of measurements of side-channel related phenomena of the digital device, such as power draw or electromagnetic emissions is obtained. A second time sequence of debug outputs of the digital device, such as program counter contents or other device processor or register states, is obtained. The first time sequence and the second time sequence are obtained based on a common time reference, and thus correlated in time. A controller can provide a common timing signal to measurement equipment obtaining the first time sequence and to a debug tool obtaining the second time sequence, and the common time reference can be correspond to the common timing signal.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: November 7, 2023
    Assignee: Newae Technology Inc
    Inventors: Jean-Pierre Thibault, Colin Patrick O'Flynn
  • Publication number: 20220108021
    Abstract: A method and apparatus for analyzing side-channel security vulnerabilities in a digital device. A first time sequence of measurements of side-channel related phenomena of the digital device, such as power draw or electromagnetic emissions is obtained. A second time sequence of debug outputs of the digital device, such as program counter contents or other device processor or register states, is obtained. The first time sequence and the second time sequence are obtained based on a common time reference, and thus correlated in time. A controller can provide a common timing signal to measurement equipment obtaining the first time sequence and to a debug tool obtaining the second time sequence, and the common time reference can be correspond to the common timing signal.
    Type: Application
    Filed: October 6, 2020
    Publication date: April 7, 2022
    Inventors: JEAN-PIERRE THIBAULT, COLIN PATRICK O'FLYNN
  • Publication number: 20180044924
    Abstract: A decking system facilitates runoff by creation of lengthwise conduits in overlapping planks when assembled. The system includes a plurality of decking planks each having a main section elongated between a first end and a second end. A top connection flange has a proximal section coplanar with a top surface of the plank and a distal section extending perpendicularly from the proximal section defining a downwardly facing channel. A bottom connection flange has a first portion coplanar with the bottom surface of the plank and a second portion extending perpendicularly from the first portion defining an upwardly facing channel. A length of the proximal section is greater than a thickness of the second portion to define a conduit therebetween when a pair of the planks are adjacently positioned with the top connection flange overlapping the bottom connection flange.
    Type: Application
    Filed: August 9, 2016
    Publication date: February 15, 2018
    Inventor: Patrick O. Flynn
  • Publication number: 20170067961
    Abstract: Methods and apparatus are provided for determining if an embedded system or integrated circuit is operating correctly, or if the device is faulty or counterfeit. Measurements of power consumption are used to determine the state of the device under test, these measurements being performed at multiple operating or environmental conditions to increase the ability of the apparatus to detect faulty and counterfeit devices.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 9, 2017
    Applicant: NEWAE TECHNOLOGY INC.
    Inventor: Colin Patrick O'Flynn
  • Patent number: 9429624
    Abstract: Methods and apparatus are provided for sampling an indicator of the internal state of an embedded system or integrated circuit, where the indicator is sampled in a manner synchronous to the internal clock of the embedded system or integrated circuit. The resulting samples can be used for determining secret data within the embedded system or integrated circuit, detecting failures, or detecting counterfeit devices.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: August 30, 2016
    Inventor: Colin Patrick O'Flynn
  • Publication number: 20150301109
    Abstract: Methods and apparatus are provided for sampling an indicator of the internal state of an embedded system or integrated circuit, where the indicator is sampled in a manner synchronous to the internal clock of the embedded system or integrated circuit. The resulting samples can be used for determining secret data within the embedded system or integrated circuit, detecting failures, or detecting counterfeit devices.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 22, 2015
    Inventor: Colin Patrick O'Flynn
  • Publication number: 20150223323
    Abstract: A PCB footprint consisting of a plurality of pads, positioned such that many different electronic components can be mounted which would otherwise require a custom circuit board. One or more of the leads can be connected via a low-impedance path to a ground plane, making a suitable platform for prototyping high-frequency designs.
    Type: Application
    Filed: February 5, 2014
    Publication date: August 6, 2015
    Inventor: Colin Patrick O'Flynn
  • Patent number: 8245481
    Abstract: A method of forming a deck may comprise forming components for the deck at a first location, including forming components of a perimeter support frame for the deck to extend along a perimeter of the deck. The components of the perimeter support frame may include a plurality of perimeter frame assemblies, and forming components of an interstitial support frame for the deck to position in the perimeter support frame. The components may be transported to a location where the deck is to be used. The method may include assembling the components of the deck to form the deck at the location. The assembling step may include assembling the perimeter support frame from the perimeter frame assemblies, assembling the interstitial support frame in the perimeter support frame, and assembling decking elements on the support frames to form a floor of the deck. A kit for the deck is also disclosed.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: August 21, 2012
    Inventor: Patrick O. Flynn
  • Patent number: D972749
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: December 13, 2022
    Inventor: Patrick O. Flynn