Abstract: Active matrix display module (10) comprising a driving circuit with a source driver (20) and a gate driver (12). Furthermore, a display panel (11) with pixels consisting of three sub-pixels is provided. The sub-pixels are arranged in rows and columns and each sub-pixel comprises a sub-pixel selection transistor arranged at an intersection of a row and a column. The gate driver (12) is employed to select and deselect all pixels of a row of the display panel (11) and the source driver (20) is employed for providing the required voltage levels to all sub-pixels of a currently selected row, said voltage levels corresponding to the desired intensity for each color. Demultiplexer switches (21) are integrated onto the display panel (11) for demultiplexing columns of the display panel (11). The active matrix display module (10) further comprises means (18) for color shift compensation. These means (18) implement a selection order for the selection of the sub-pixels to compensate unintentional color shifts.

Abstract: Active matrix display module (10) comprising a driving circuit with a source driver (20) and a gate driver (12). Furthermore, a display panel (11) with pixels consisting of three sub-pixels is provided. The sub-pixels are arranged in rows and columns and each sub-pixel comprises a sub-pixel selection transistor arranged at an intersection of a row and a column. The gate driver (12) is employed to select and deselect all pixels of a row of the display panel (11) and the source driver (20) is employed for providing the required voltage levels to all sub-pixels of a currently selected row, said voltage levels corresponding to the desired intensity for each color. Demultiplexer switches (21) are integrated onto the display panel (11) for demultiplexing columns of the display panel (11). The active matrix display module (10) further comprises means (18) for color shift compensation. These means (18) implement a selection order for the selection of the sub-pixels to compensate unintentional color shifts.

Abstract: The invention concerns an arrangement on a semiconductor chip for calibrating temperature setting curve having a signal generation unit (2) for providing a first signal (Iptat1, Vptat1, fptat1), which is proportional to the actual uncalibrated temperature T1 of the chip. To avoid bringing the chip on a second temperature it is proposed to read a first signal (Iptat1, Vptat1, fptat1), which is proportional to the actual uncalibrated temperature T1 of the chip and generate a signal offset (Ivirt, Vvirt, fvirt), which is combined with the first signal (Iptat1, Vptat1, fptat1) defining a second signal (Iptat2, Vptat2, fptat2) and to extract a first actual temperature T1 from the first signal (Iptat1, Vptat1, fptat1) and a second uncalibrated temperature T2 from the second signal (Iptat2, Vptat2, fptat2).

Abstract: A display device (1) comprising: a liquid crystal display (2) having pixels (8) which are arranged in columns C and rows R; and a gate driving arrangement (4) for activating the pixels (8) of rows (R) in dependence on a row scanning scheme; a source driving arrangement (3) for providing column voltages representing the respective image data, a number of buffers (40) depending on the number of grey levels for supplying the respective voltage levels to the columns (C), a switching unit (31) for selecting a voltage level which corresponds to the grey level to be displayed; and a control unit (32) for controlling the buffers (40). For reducing the power consumption, an analyzing unit (39) is provided which analyzes the image data to be displayed such that the control unit (32) can determine the number of required buffers in dependence on the number of grey levels to be displayed and can switch off any unused buffers.

Abstract: The invention concerns an arrangement on a semiconductor chip for calibrating temperature setting curve having a signal generation unit (2) for providing a first signal (Iptat1, Vptat1, fptat1), which is proportional to the actual uncalibrated temperature T1 of the chip. To avoid bringing the chip on a second temperature it is proposed to read a first signal (Iptat1, Vptat1, fptat1), which is proportional to the actual uncalibrated temperature T1 of the chip and generate a signal offset (Ivirt, Vvirt, fvirt), which is combined with the first signal (Iptat1, Vptat1, fptat1) defining a second signal (Iptat2, Vptat2, fptat2) and to extract a first actual temperature T1 from the first signal (Iptat1, Vptat1, fptat1) and a second uncalibrated temperature T2 from the second signal (Iptat2, Vptat2, fptat2).

Abstract: A display device (1) comprising: a liquid crystal display (2) having pixels (8) which are arranged in columns C and rows R; and a gate driving arrangement (4) for activating the pixels (8) of rows (R) in dependence on a row scanning scheme; a source driving arrangement (3) for providing column voltages representing the respective image data, a number of buffers (40) depending on the number of grey levels for supplying the respective voltage levels to the columns (C), a switching unit (31) for selecting a voltage level which corresponds to the grey level to be displayed; and a control unit (32) for controlling the buffers (40). For reducing the power consumption, an analyzing unit (39) is provided which analyzes the image data to be displayed such that the control unit (32) can determine the number of required buffers in dependence on the number of grey levels to be displayed and can switch off any unused buffers.