Abstract: A method for assisting window selection in a graphical user interface determines one or more current top-level windows to be displayed to a user for selection by the user. The user is then able to select a particular window of the one or more windows being displayed. In some embodiments, the one or more current top-level windows are displayed as translucent windows. Additionally, in some embodiments, a user is able to cycle through multiple sets of one or more windows in order to locate a particular window.

Abstract: A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Abstract: A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process-compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Abstract: An improved instruction decoder is described which uses parallel stages which operate in a pipeline fashion. The decoder is particularly useful in a microprocessor which has variable length instructions. The first stage decodes the OP code and register and address mode specifier fields while the second stage directs the sequencing of address calculations. The first two lines of microcode are provided by the first stage as well as a look up to microcode in the microcode memory.

Abstract: An improved scheme for generating a carry lookahead is described. An irregular grouping, wherein large bit groups are used in the middle and shorter bit groups are used at the ends, provides for a reduction in carry propagation delay.