Abstract: Disclosed examples include amplifier circuits with a first stage to amplify an input voltage signal according to a first stage gain to provide a first stage output voltage signal, and a second stage to provide an amplifier output voltage signal. A bias circuit provides an amplifier bias current signal to a current mirror circuit coupled with the first stage to control a first stage bias current, and an adjustment circuit to reduce the amplifier bias current signal and increase the first stage gain when the input voltage signal is near a first supply voltage or a second supply voltage.

Abstract: Disclosed examples include amplifier circuits with a first stage to amplify an input voltage signal according to a first stage gain to provide a first stage output voltage signal, and a second stage to provide an amplifier output voltage signal. A bias circuit provides an amplifier bias current signal to a current mirror circuit coupled with the first stage to control a first stage bias current, and an adjustment circuit to reduce the amplifier bias current signal and increase the first stage gain when the input voltage signal is near a first supply voltage or a second supply voltage.

Abstract: A class DH amplifier is provided. The amplifier is generally comprised of a tracking power supply, a class D amplifier section, and a carrier generator. The tracking power supply receives a supply voltage and an analog input signal, and the tracking power supply provides an input for the carrier generator. Based on its input from the tracking power supply, the carrier generator can output a positive ramp signal and a negative ramp signal to the class D amplifier section. The class D amplifier section can generate an output signal base on the analog input signal and the ramp signals from the carrier generator.

Abstract: Recently, there has been an increased desire to measure load currents of class-D amplifiers to improve performance. The traditional solution has been to include one or more discrete components in series with the load, but this degrades performance. Here, however, circuit is provided (which includes sample-and-hold circuit) that accurately measures load currents without inhibiting performance and that is not inhibited by the phase differences between the load voltage and load current.

Abstract: Recently, there has been an increased desire to measure load currents of class-D amplifiers to improve performance. The traditional solution has been to include one or more discrete components in series with the load, but this degrades performance. Here, however, circuit is provided (which includes sample-and-hold circuit) that accurately measures load currents without inhibiting performance and that is not inhibited by the phase differences between the load voltage and load current.

Abstract: A class DH amplifier is provided. The amplifier is generally comprised of a tracking power supply, a class D amplifier section, and a carrier generator. The tracking power supply receives a supply voltage and an analog input signal, and the tracking power supply provides an input for the carrier generator. Based on its input from the tracking power supply, the carrier generator can output a positive ramp signal and a negative ramp signal to the class D amplifier section. The class D amplifier section can generate an output signal base on the analog input signal and the ramp signals from the carrier generator.

Abstract: A system and method for driving a load at a desired operating level. A driver is connected to a load. The load can be selected from a plurality of loads by a selection system, such as a multiplexer, or a single load can be utilized. Feedback from the load is provided to the driver for achieving the desired operating level. A zero temperature coefficient resistance formed by two resistors having different resistances can be used so that the driver emulates an ideal resistor having a substantially zero temperature coefficient, providing a temperature independent current to the load.

Abstract: A circuit topology for gain boosted high-swing folded cascode has been improved to maximize the available dynamic range in applications having low supply voltage requirements. The circuit includes an improved gain boost amplifier that maximizes the available dynamic range for applications having low supply voltage requirements. The improved gain boosting amplifier includes a differential pair of input transistors connected to a current mirror, wherein a pair of current sources supply current to each lead of the current mirror. One lead of the current mirror is level-shifted by a transistor coupled to another current source, wherein the coupling of the transistor and the current source form the output of the amplifier. Effectively, the amplifier consists of a level shifter and a series common-drain, common-gate amplifier. A reduction in transconductance gm from the series combination is compensated by a current mirror ratio (K:1) between the level shift and the common-drain, common-gate amplifier.

Abstract: A control voltage window generator that tracks process, voltage supply, and temperature variations for a voltage controlled oscillator includes: a first transistor of a first conductivity type coupled between a supply voltage node and an upper control voltage node; and a second transistor of a second conductivity type coupled to the upper control voltage node to compensate for process variations in devices of the first conductivity type. Additionally, a target pull-in voltage generator includes circuitry for providing a pull-in control voltage that will always be inside the control voltage window, and also tracks process, voltage supply, and temperature variations.

Abstract: A gain controlled voltage controlled oscillator. A current controlled oscillator is adapted to provide an output signal oscillating at a frequency controllable by controlling a current applied thereto. A first current source provides a first control current controllable by controlling a voltage applied thereto that has a predetermined range. A first current mirror is adapted to mirror the control current to the current controlled oscillator. A second current source is adapted to provide a second control current for mirroring to the current controlled oscillator by the first current mirror when the control voltage is in a low portion of the range.

Abstract: A segmented current mode DAC (200) is disclosed herein having a current matching circuit (260) that compensates for the current mismatch produced by the transistors of each current source. This segmented current mode DAC (200) includes an input stage (210), a first and second controllable current source (270, 220), a current matching circuit (260), and an output switching network (272–274, 222–236). The first controllable current source (270) couples to receive a mirrored current as provided by the input stage (210) to provide a current source output controllable in current increments responsive to the M least significant bits for converting of the digital signal to analog form, where M is less than N. The second controllable current source (220) couples to receive the mirrored current to provide a current source output controllable in current increments responsive to the N?M most significant bits for converting of the digital signal to analog form.

Abstract: The asymmetric digital subscriber line receive channel includes: first and second external resistors 20 and 22 coupled to a telephone line 24 and 26; a coarse programmable gain amplifier CPGA formed in a low voltage process having inputs coupled to the first and second external resistors 20 and 22; and a fine programmable gain amplifier PGA1 coupled to an output of the coarse programmable gain amplifier CPGA, and having a very fine gain trim adjustment to compensate for a mismatch between the external resistors 20 and 22 and the coarse programmable gain amplifier CPGA.

Abstract: A process-insensitive, highly-linear, constant transconductance circuit employs a CMOS multiplier in the signal path that is offset biased with a specific combination of currents to compensate for variations in transconductance due to resistor processing variations.

Abstract: A process-insensitive, highly-linear, constant transconductance circuit employs a CMOS multiplier in the signal path that is offset biased with a specific combination of currents to compensate for variations in transconductance due to resistor processing variations.

Abstract: The asymmetric digital subscriber line receive channel includes: first and second external resistors 20 and 22 coupled to a telephone line 24 and 26; a coarse programmable gain amplifier CPGA formed in a low voltage process having inputs coupled to the first and second external resistors 20 and 22; and a fine programmable gain amplifier PGA1 coupled to an output of the coarse programmable gain amplifier CPGA, and having a very fine gain trim adjustment to compensate for a mismatch between the external resistors 20 and 22 and the coarse programmable gain amplifier CPGA.

Abstract: A hard disk drive system (10) includes a read/write head (21) for reading and writing data to and from a rotating magnetic disk (12). The read/write head includes a portion which is a magneto-resistive read head (36), the output of which is supplied through a preamplifier (26) to a read channel circuit (27). The read head has a nonlinear transfer function. The read channel circuit includes an asymmetry compensation circuit (62), which generates an analog compensation signal by squaring an output signal from the read head and scaling by an asymmetry factor (.alpha.'). The analog compensation signal is combined with the analog output signal in order to obtain a corrected analog signal, which is substantially free of the distortion introduced by the read head.

Abstract: A method for generating a response in a transconductance circuit includes receiving a circuit differential voltage input and providing a differential voltage input to each of a plurality of differential pairs to control, in part, a differential current generated by each differential pair. Each differential voltage input has a different common-mode voltage level. The method also includes sinking current through each of the differential pairs to control the differential current generated by each differential pair. The magnitude of the current sunk through one of the differential pairs is different from the magnitude of the current sunk through at least one of the other differential pairs. The method also includes combining the generated differential current from each of the plurality of differential pairs to produce a differential current output.

Abstract: A hard disk drive system (10) has a read/write head (12) coupled to a read channel circuit (23) in an integrated circuit (13). The read channel circuit includes a bipolar transconductance-C filter (26) having at least one capacitor (27) with a capacitance value that may vary from an intended value. A temperature compensating voltage (VPTAT) is converted to a first current, a programming circuit (51) produces a second current (IPROG) as a function of the first current and a digital compensating input (54), and the second current is converted to a voltage (61) and used to control characteristics of the filter circuit. A trimming circuit (46) shunts away from the programming circuit a portion of the current generated by the voltage-to-current converter circuit, which portion is defined by a digital trim input (48).

Abstract: A programmably variable transconductance circuit (10) and method for varying its transconductance includes first and second current control input devices (16, 18), each having an input (17,19) to which a differential input voltage may be applied. A pair of current steering circuits (26, 28, 30, 32) are each connected in series with a respective one of the first and second current control devices (16, 18) for dividing respective currents in the first and second current control devices (16, 18) between a differential output current path (12, 14) and another current flow path, and a programmable voltage source (90) supplying V.sub.CONTROL is connected to control the current division by the current steering circuits (26, 28, 30, 32). The programmable voltage, V.sub.CONTROL, is provided by a programmable current control loop (90), which incorporates a master transconductance circuit, to establish a constant transconductance independently of temperature variations.

Abstract: A programmable, electronic filter (10) includes a memory device such as a Read Only Memory ROM (22) for storing specific cut-off frequency adjustment data corresponding to various cut-off frequencies. The ROM (22) receives a ROM address (28) corresponding to a cut-off frequency signal (26). The ROM (22) generates a specific cut-off frequency adjustment value (30) for a digital-to-analog convertor (20) to produce an output reference current (34). A reference voltage (40), an error amplifier (14), a master transconductance element (16), and a capacitor (18) serve as a tuning loop and ultimately produce a control signal (38) in response to the output reference current (34). Control signal (38) serves as an input to slave filter (12) along with the cut-off frequency signal (26). The slave filter (12) may then serve as an electronic filter having the desired frequency-response characteristic.