Patents by Inventor Patrick Peter Elizabeth Meuwissen
Patrick Peter Elizabeth Meuwissen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8510534Abstract: A scalar/vector processor includes a plurality of functional units (252, 260, 262, 264, 266, 268, 270). At least one of the functional units includes a vector section (210) for operating on at least one vector and a scalar section (220) for operating on at least one scalar. The vector section and scalar section of the functional unit co-operate by the scalar section being arranged to provide and/or consume at least one scalar required by and/or supplied by the vector section of the functional unit.Type: GrantFiled: May 22, 2003Date of Patent: August 13, 2013Assignee: ST-Ericsson SAInventors: Cornelis Hermanus Van Berkel, Patrick Peter Elizabeth Meuwissen, Nur Engin
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Patent number: 8240854Abstract: An autostereoscopic display device includes a reflection layer for reflecting at least a portion of incident light, a polarization conversion layer arranged over the reflection layer, and an array of lenticular elements arranged over at least a portion of the polarization conversion layer and including a birefringent material. Light having a first state of polarization is configured to pass through the lenticular element array without substantial lenticular element focusing, where the polarization state is transformed by the polarization conversion layer such that the reflected light has a second state of polarization. Light having the second polarization state passes through the lenticular element array with the lenticular element focusing to provide multiple views to different viewing locations.Type: GrantFiled: December 12, 2007Date of Patent: August 14, 2012Assignee: Koninlijke Philips Electronics N.V.Inventors: Marcellinus Petrus Carolus Michael Krijn, Patrick Peter Elizabeth Meuwissen, Hans Zuidema, Willem Lubertus Ijzerman, Siebe Tjerk De Zwart, Oscar Hendrikus Willemsen
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Patent number: 7797493Abstract: The present invention relates to a data processing device (10) comprising a processing unit (12) and a memory unit (14), and to a method for controlling operation of a memory unit (14) of a data processing device. The memory unit (14) comprises a main memory (16), a low- level cache memory (20.2), which is directly connected to the processing unit (12) and adapted to hold all pixels of a currently active sliding search area for reading access by the processing unit (12), a high-level cache memory (18), which is connected between the low-level cache memory and the frame memory, and a first pre-fetch buffer (20.1), which is connected between the high-level cache memory and the low- level cache memory and which is adapted to hold one search-area column or one search-area line of pixel blocks, depending on the scan direction and scan order followed by the processing unit. Reading and fetching functionalities are decoupled in the memory unit (14).Type: GrantFiled: February 13, 2006Date of Patent: September 14, 2010Assignee: Koninklijke Philips Electronics N.V.Inventors: Harm Johannes Antonius Maria Peters, Ramanathan Sethuraman, Gerard Veldman, Patrick Peter Elizabeth Meuwissen
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Patent number: 7694078Abstract: An array of data values, such as an image of pixel values, is stored in a main memory (12). A processing operation is performed using the pixel values. The processing operation defines time points of movement of a multidimensional region (20, 22) of locations in the image. Pixel values from inside and around the region are cached for processing. At least when a cache miss occurs for a pixel value from outside the region, cache replacement of data in cache locations (142) is performed. Locations that store pixel data for locations in the image outside the region (20, 22) are selected for replacement, selectively exempting from replacement cache locations (142) that store pixel data locations in the image inside the region. In embodiments, different types of cache structure are used for caching data values inside and outside the region. In an embodiment the cache locations for pixel data inside the regions support a higher level of output parallelism than the cache locations for pixel data around the region.Type: GrantFiled: April 21, 2005Date of Patent: April 6, 2010Assignee: Silicon Hive B.V.Inventors: Ramanathan Setheraman, Aleksandar Beric, Carlos Antonio Alba Pinto, Harm Johannes Antonius Maria Peters, Patrick Peter Elizabeth Meuwissen, Srinivasan Balakrishnan, Gerard Veldman
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Patent number: 7684832Abstract: To achieve a shortening of the initial synchronization time and/or extension of the stand-by time with a method of connecting an UMTS mobile radio to a network, the UMTS mobile radio receives and stored in one or more time-limited RF receive windows the signals that are subsequently evaluated when the HF receiver is switched off.Type: GrantFiled: May 19, 2003Date of Patent: March 23, 2010Assignee: ST-Ericsson SAInventors: Frank Heinle, Axel Hertwig, Cornelis Hermanus Van Berkel, Patrick Peter Elizabeth Meuwissen
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Publication number: 20100033680Abstract: An autostereoscopic display device comprises a reflection layer for reflecting at least a portion of incident light, a polarization conversion layer arranged over the reflection layer, and an array of lenticular elements arranged over at least a portion of the polarization conversion layer and including a birefringent material. Light having a first state of polarization is arranged to pass through the lenticular element array without substantial lenticular element focusing, wherein the polarization state is transformed by the polarization conversion layer such that the reflected light has a second state of polarization arranged to pass through the lenticular element array with lenticular element focusing to provide multiple views.Type: ApplicationFiled: December 12, 2007Publication date: February 11, 2010Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Marcellinus Petrus Carolus Michael Krijn, Patrick Peter Elizabeth Meuwissen, Hans Zuidema, Willem Lubertus Ijzerman, Siebe Tjerk De Zwart, Oscar Hendrikus Willemsen
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Publication number: 20100026797Abstract: A display device (2) for displaying a scene (104) comprising a shared image component (102) and a private image component (106), wherein the display device is adapted to display a plurality of perspectives of the shared image component and a plurality of views of each of the plurality of perspectives such that a multi-view perspective (P1; P2) of the shared image component is visible at each of a plurality of viewing zones, the display device being further adapted to display the private image component such that it is visible at one or more, but not all of the viewing positions.Type: ApplicationFiled: December 19, 2007Publication date: February 4, 2010Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.Inventors: Patrick Peter Elizabeth Meuwissen, Abraham Karel Riemens, Siebe TJerke De Zwart, Ingrid Emilieene Joanna Rita Heynderickx
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Publication number: 20080282038Abstract: An array of data values, such as an image of pixel values, is stored in a main memory (12). A processing operation is performed using the pixel values. The processing operation defines time points of movement of a multidimensional region (20, 22) of locations in the image. Pixel values from inside and around the region are cached for processing. At least when a cache miss occurs for a pixel value from outside the region, cache replacement of data in cache locations (142) is performed. Locations that store pixel data for locations in the image outside the region (20, 22) are selected for replacement, selectively exempting from replacement cache locations (142) that store pixel data locations in the image inside the region. In embodiments, different types of cache structure are used for caching data values inside and outside the region. In an embodiment the cache locations for pixel data inside the regions support a higher level of output parallelism than the cache locations for pixel data around the region.Type: ApplicationFiled: April 21, 2005Publication date: November 13, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.Inventors: Ramanathan Sethuraman, Aleksandar Beric, Carlos Antonio Alba Pinto, Harm Johannes Antonius Maria Peters, Patrick Peter Elizabeth Meuwissen, Srinivasan Balakrishnan, Gerard Veldman
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Patent number: 7430631Abstract: A processing system includes a processor and a physical memory (500) with a single-size memory port (505) for accessing data in the memory. The processor is arranged to operate on data of at least a first data size and a smaller second data size. The first data size is equal to or smaller than the size of memory port. The processing system including at least one data register (514) of the first data size connected to the memory port (505), and at least one data port (525) of the second data size connected to the data register (525) and the processor for enabling access to data elements of the second size.Type: GrantFiled: May 7, 2003Date of Patent: September 30, 2008Assignee: NXP B.V.Inventors: Cornelis Hermanus Van Berkel, Patrick Peter Elizabeth Meuwissen
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Publication number: 20080147980Abstract: The present invention relates to a data processing device (10) comprising a processing unit (12) and a memory unit (14), and to a method for controlling operation of a memory unit (14) of a data processing device. The memory unit (14) comprises a main memory (16), a low- level cache memory (20.2), which is directly connected to the processing unit (12) and adapted to hold all pixels of a currently active sliding search area for reading access by the processing unit (12), a high-level cache memory (18), which is connected between the low-level cache memory and the frame memory, and a first pre-fetch buffer (20.1), which is connected between the high-level cache memory and the low- level cache memory and which is adapted to hold one search-area column or one search-area line of pixel blocks, depending on the scan direction and scan Reading and fetching functionalities are decoupled in the memory unit (14).Type: ApplicationFiled: February 13, 2006Publication date: June 19, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.Inventors: Harm Johannes Antonius Maria Peters, Ramanathan Sethuraman, Gerard Veldman, Patrick Peter Elizabeth Meuwissen
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Patent number: 7383419Abstract: A processor includes a memory port for accessing a physical memory under control of an address. A processing unit executing instructions stored in the memory and/or operates on data stored in the memory. An address generation unit (“AGU”) generates address for controlling access to the memory; the AGU being associated with a plurality of N registers enabling the AGU to generate the address under control of an address generation mechanism. A memory unit is operative to save/load k of the N registers, where 2<=k<=N, triggered by one operation. To this end, the memory unit includes a concatenator for concatenating the k registers to one memory word to be written to the memory through the memory port and a splitter for separating a word read from the memory through the memory port into the k registers.Type: GrantFiled: May 7, 2003Date of Patent: June 3, 2008Assignee: NXP B.V.Inventors: Cornelis Hermanus Van Berkel, Patrick Peter Elizabeth Meuwissen
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Publication number: 20080059551Abstract: Configurable vector processors can be equipped with code generators, so that they are capable of handling different standards and codes. Furthermore, they can be arranged to provide support for related functions such as cyclic redundancy check (CRC). A configurable vector processor would then be equipped with a plurality of generators which generate basic codes in vector format. However, a disadvantage of such a configurable vector processor is that it cannot provide a composite code which is dependent on such basic codes. This is necessary if the configurable vector processors should be flexible enough to support a variety of CDMA-like standards. The device according to the invention is provided with at least two weighted sum units, which are able to make a selection out of a plurality of incoming basic-code vectors by means of a weighted sum operation, under the control of a configuration word.Type: ApplicationFiled: July 13, 2004Publication date: March 6, 2008Inventors: Cornelis Hermanus Van Berkel, Patrick Peter Elizabeth Meuwissen, Ricky Johannes Maria Nas