Abstract: A low-EMI switched circuit comprises two or more switches, wherein impedance transitions of the switches are overlapped and the overlap is varied using variable switch timing based on an output power level of the switched circuit. The variable timing results in a variable impedance overlap between the switches. In one example, when one switch turns off (begins a low to high impedance transition) and a second switch turns on (begins a high to low impedance transition), a greater timing delay in beginning the second switch's transition results in a higher switch impedance overlap than a shorter delay does. If the variable timing is based on output power of the switched circuit, the variable delay can operate to reduce fly-back voltages at high power output levels and reduce shoot-through current at lower power levels, reducing EMI and quiescent current of the switched circuit.

Abstract: A low-EMI switched circuit comprises two or more switches, wherein impedance transitions of the switches are overlapped and the overlap is varied using variable switch timing based on an output power level of the switched circuit. The variable timing results in a variable impedance overlap between the switches. In one example, when one switch turns off (begins a low to high impedance transition) and a second switch turns on (begins a high to low impedance transition), a greater timing delay in beginning the second switch's transition results in a higher switch impedance overlap than a shorter delay does. If the variable timing is based on output power of the switched circuit, the variable delay can operate to reduce fly-back voltages at high power output levels and reduce shoot-through current at lower power levels, reducing EMI and quiescent current of the switched circuit.

Abstract: Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time.

Abstract: Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time.

Abstract: Precision integrated time reference circuits are disclosed. Preferred embodiments provide time reference circuits that are relatively insensitive to variations in process, supply, and temperature. A preferred embodiment of the invention is disclosed in which a relaxation oscillator according to the invention includes a reference voltage circuit configured to maintain a reference voltage in proportion to actual circuit resistance values. Aspects of the invention also include dynamic compensation for variations in temperature.

Abstract: A voltage controlled oscillator (600) includes a voltage to current portion (400) that is inversely proportional to the semiconductor processing in order to compensate for variations both in the low-frequency and high-frequency portions of the VCO gain response. To compensate for low-frequency variations, a portion of the control current (ICTL), non-compensated control current ICTLNC (436), is subtracted from a reference current IREF (408) and the result, a low-frequency compensating control current, ICTLLF (438), is added to the non-compensated control current ICTLNC (436). To compensate for high frequency variations, a number of differential transistor pairs (410-416) are provided that have tail currents that are inversely proportional to the processing. One input (426) to all the differential pairs is connected to the VCO's control voltage while the other inputs (418-424) are connected to successively increasing voltages in the control voltage range.

Abstract: A voltage controlled oscillator (600) includes a voltage to current portion (400) that is inversely proportional to the semiconductor processing in order to compensate for variations both in the low-frequency and high-frequency portions of the VCO gain response. To compensate for low-frequency variations, a portion of the control current (ICTL), non-compensated control current ICTLNC (436), is subtracted from a reference current IREF (408) and the result, a low-frequency compensating control current, ICTLLF (438), is added to the non-compensated control current ICTLNC (436). To compensate for high frequency variations, a number of differential transistor pairs (410-416) are provided that have tail currents that are inversely proportional to the processing. One input (426) to all the differential pairs is connected to the VCO's control voltage while the other inputs (418-424) are connected to successively increasing voltages in the control voltage range.