Abstract: According to various aspects, a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode includes: a first electrode layer including a first material having a first microstructure; a functional layer in direct contact with the first electrode layer; and a second electrode layer in direct contact with the functional layer, the second electrode layer including a second material having a second microstructure different from the first microstructure.

Abstract: A memory cell includes a capacitive memory structure comprising a first electrode; a field-effect transistor structure comprising a gate electrode; one or more insulator layers; one or more source/drain contact structures embedded in the one or more insulator layers to electrically contact the field-effect transistor structure; and a connection structure embedded in at least one of the one or more insulator layers; and one or more electrically insulating structures in addition to the one or more insulator layers configured to prevent a leakage current-induced charging of the first electrode, the gate electrode, and the connection structure, wherein the one or more electrically insulating structures comprise: a memory charge-prevention layer disposed between the first electrode of the capacitive memory structure and at least one of the one or more insulator layers, the memory charge-prevention layer laterally surrounding the first electrode of the capacitive memory structure.

Abstract: The present invention relates to an integrated electronic circuit and method of making comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).

Abstract: According to various aspects, a method of forming one or more remanent-polarizable capacitive structures, the method including forming one or more capacitive structures, each of the one or more capacitive structures includes: one or more electrodes, one or more precursor structures disposed adjacent to the one or more electrodes, wherein each of the one or more precursor structures has a first dimension in a range from about 1 nm to 100 nm and a second dimension in a range from about 1 nm to about 30 nm; and, subsequently, forming one or more remanent-polarizable structures comprising a crystalline remanent-polarizable material based on a crystallization of a precursor material of the one or more precursor structures.

Abstract: A movable piezo element and to a method for producing the element are provided. The movable piezo element may have a structured substrate, in which an intermediate layer is arranged between a first substrate layer and a second substrate layer. The element may also have a first electrode layer. The element may also have a second electrode layer arranged on the ferroelectric, piezoelectric, or flexoelectric layer. The second substrate layer may be structured such that at least one bar of the second substrate layer is formed. The bar may be clamped on one side and may be physically spaced from the first substrate layer. A surface of the bar facing away from the first substrate layer, and/or a lateral surface of the bar, may be at least partly covered by another layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to ferroelectric based transistors and methods of manufacture. The ferroelectric based transistor includes: a semiconductor-on-insulator substrate including a semiconductor material, a buried insulator layer under the semiconductor material and a substrate material under the semiconductor channel material; a ferroelectric capacitor under the buried insulator layer and which includes a bottom electrode, a top electrode and a ferroelectric material between the bottom electrode and the top electrode; a gate stack over the semiconductor material; a first terminal contact connecting to the bottom electrode of the ferroelectric capacitor; and a second terminal contact connecting to the top electrode of the ferroelectric capacitor.

Abstract: According to various aspects, a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode includes: a first electrode layer including a first material having a first microstructure; a functional layer in direct contact with the first electrode layer; and a second electrode layer in direct contact with the functional layer, the second electrode layer including a second material having a second microstructure different from the first microstructure.

Abstract: According to various aspects, a memory cell is provided, the memory cell including: a capacitive memory structure, the capacitive memory structure including a first electrode, a second electrode, and a memory structure disposed between the first electrode and the second electrode; and a field effect transistor structure, the field effect transistor structure including a gate structure coupled to the capacitive memory structure, wherein the first electrode of the capacitive memory structure includes a first electrode material having a first work-function and the second electrode of the capacitive memory structure includes a second electrode material having a second work-function, wherein the first work-function is different from the second work-function.

Abstract: According to various aspects, a method of forming one or more remanent-polarizable capacitive structures, the method including forming one or more capacitive structures, each of the one or more capacitive structures includes: one or more electrodes, one or more precursor structures disposed adjacent to the one or more electrodes, wherein each of the one or more precursor structures has a first dimension in a range from about 1 nm to 100 nm and a second dimension in a range from about 1 nm to about 30 nm; and, subsequently, forming one or more remanent-polarizable structures comprising a crystalline remanent-polarizable material based on a crystallization of a precursor material of the one or more precursor structures.

Abstract: According to various aspects, a memory cell is provided, the memory cell including: a capacitive memory structure including a first electrode; a field-effect transistor structure including a gate electrode; one or more insulator layers, one or more source/drain contact structures embedded in the one or more insulator layers to electrically contact the field-effect transistor structure, and a connection structure embedded in at least one of the one or more insulator layers, wherein the connection structure electrically conductively connects the first electrode of the capacitive memory structure and the gate electrode of the field-effect transistor structure with one another and is electrically floating, and one or more additional electrically insulating structures configured to prevent a leakage current-induced charging of the first electrode, the gate electrode, and the connection structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to ferroelectric based transistors and methods of manufacture. The ferroelectric based transistor includes: a semiconductor-on-insulator substrate including a semiconductor material, a buried insulator layer under the semiconductor material and a substrate material under the semiconductor channel material; a ferroelectric capacitor under the buried insulator layer and which includes a bottom electrode, a top electrode and a ferroelectric material between the bottom electrode and the top electrode; a gate stack over the semiconductor material; a first terminal contact connecting to the bottom electrode of the ferroelectric capacitor; and a second terminal contact connecting to the top electrode of the ferroelectric capacitor.

Abstract: The present invention relates to a voltage-controllable capacitor comprising a first electrode layer (4) composed of a non-ferroelectric material, said first electrode layer being applied on a substrate (6), a ferroelectric interlayer (3) having a thickness that is less than the thickness of the first electrode layer (4), and a second electrode layer (2) composed of a non-ferroelectric material. The ferroelectric interlayer (3) is arranged between the first electrode layer (4) and the second electrode layer (2).

Abstract: The present invention relates to an integrated electronic circuit and method of making comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).

Abstract: The present invention relates to an integrated electronic circuit comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).

Abstract: The invention relates to a method for manufacturing a microelectronic circuit. A substrate is provided. A source contact, a bulk contact and a drain contact are each produced for a transistor and for a memory transistor. In a respective common step, an insulating layer of the transistor and an insulating layer of the memory transistor as well as a metal layer of the transistor and a metal layer of the memory transistor are produced. At least one capacitor is produced as part of the memory transistor. Gate contacts connected to the metal layer of the transistor and connected to a metal layer of the capacitor of the memory transistor, respectively, are produced. Furthermore, the invention relates to a microelectronic circuit.

Abstract: The present invention relates to a voltage-controllable capacitor comprising a first electrode layer (4) composed of a non-ferroelectric material, said first electrode layer being applied on a substrate (6), a ferroelectric interlayer (3) having a thickness that is less than the thickness of the first electrode layer (4), and a second electrode layer (2) composed of a non-ferroelectric material. The ferroelectric interlayer (3) is arranged between the first electrode layer (4) and the second electrode layer (2).

Abstract: The present invention relates to an integrated electronic circuit comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).

Abstract: The invention relates to a method for manufacturing a microelectronic circuit. A substrate is provided. A source contact, a bulk contact and a drain contact are each produced for a transistor and for a memory transistor. In a respective common step, an insulating layer of the transistor and an insulating layer of the memory transistor as well as a metal layer of the transistor and a metal layer of the memory transistor are produced. At least one capacitor is produced as part of the memory transistor. Gate contacts connected to the metal layer of the transistor and connected to a metal layer of the capacitor of the memory transistor, respectively, are produced. Furthermore, the invention relates to a microelectronic circuit.

Abstract: The invention relates to a method for manufacturing a microelectronic circuit. A substrate is provided. A source contact, a bulk contact and a drain contact are each produced for a transistor and for a memory transistor. In a respective common step, an insulating layer of the transistor and an insulating layer of the memory transistor as well as a metal layer of the transistor and a metal layer of the memory transistor are produced. At least one capacitor is produced as part of the memory transistor. Gate contacts connected to the metal layer of the transistor and connected to a metal layer of the capacitor of the memory transistor, respectively, are produced. Furthermore, the invention relates to a microelectronic circuit.

Abstract: The invention relates to a method for manufacturing a microelectronic circuit. A substrate is provided. A source contact, a bulk contact and a drain contact are each produced for a transistor and for a memory transistor. In a respective common step, an insulating layer of the transistor and an insulating layer of the memory transistor as well as a metal layer of the transistor and a metal layer of the memory transistor are produced. At least one capacitor is produced as part of the memory transistor. Gate contacts connected to the metal layer of the transistor and connected to a metal layer of the capacitor of the memory transistor, respectively, are produced. Furthermore, the invention relates to a microelectronic circuit.