Patents by Inventor Patrick QUACH

Patrick QUACH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240203664
    Abstract: Embodiments disclosed herein include a core for a package substrate. In an embodiment, the core comprises a first substrate with a first surface and a second surface, a first recess into the first surface of the first substrate, a first layer in the first recess, where the first layer is electrically conductive, a second layer over the first layer, where the second layer is a dielectric layer, and a third layer over the second layer, where the third layer is electrically conductive. In an embodiment, the core further comprises a second substrate with a third surface and a fourth surface, where the third surface of the second substrate faces the first surface of the first substrate, a second recess in the third surface of the second substrate, and a fourth layer in the second recess, where the fourth layer is electrically conductive, and the fourth layer contacts the third layer.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Inventors: Yosef KORNBLUTH, Bainye Francoise ANGOUA, Whitney BRYKS, Daniel ROSALES-YEOMANS, Aaditya Anand CANDADAI, Holly CLINGAN, Jade Sharee LEWIS, Patrick QUACH, Srinivas V. PIETAMBARAM
  • Publication number: 20240153857
    Abstract: Embodiments disclose a package substrate. In an embodiment, the package substrate comprises a core, where the core comprises: a first sub-core, where the first sub-core comprises a glass and a first through glass via (TGV), and a second sub-core, where the second sub-core comprises the glass and a second TGV. In an embodiment, the first TGV directly contacts the second TGV.
    Type: Application
    Filed: November 8, 2022
    Publication date: May 9, 2024
    Inventors: Bainye Francoise ANGOUA, Whitney BRYKS, Yosef KORNBLUTH, Daniel ROSALES-YEOMANS, Holly CLINGAN, Patrick QUACH, Jade Sharee LEWIS, Aaditya Anand CANDADAI
  • Publication number: 20230405976
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.
    Type: Application
    Filed: August 31, 2023
    Publication date: December 21, 2023
    Inventors: Jieying KONG, Gang DUAN, Srinivas PIETAMBARAM, Patrick QUACH, Dilan SENEVIRATNE
  • Patent number: 11780210
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventors: Jieying Kong, Gang Duan, Srinivas Pietambaram, Patrick Quach, Dilan Seneviratne
  • Publication number: 20210078296
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Inventors: Jieying KONG, Gang DUAN, Srinivas PIETAMBARAM, Patrick QUACH, Dilan SENEVIRATNE