Abstract: Apparatus and associated methods for a simplified multi-client initiator/target within a SAS device. Features and aspects hereof provide a simplified initiator/target component to enable cost reduction and simplification of SAS devices requiring only limited initiator/target functionality. In one embodiment, a SAS expander may incorporate simplified SSP/STP/SMP initiator/target features and aspects hereof to permit simple management of devices coupled to the expander or coupled downstream through other expanders. The simplified multi-client initiator/target suffices for simple management functions while reducing cost and complexity of the SAS expander. Features and aspects hereof may be implemented with shared circuits for each of multiple client protocols coupled with firmware operable in a general or special purpose processor embedded in the SAS device.

Abstract: The present invention is directed to a method which allows for substitution of standard SAS ALIGN primitives with an alternative, more spectrally pure set of SAS ALIGN primitives that allows for enhanced continuous adaptation performance. Two consenting SAS devices which are connected to each other may negotiate for and start communicating using the alternate set of ALIGN primitives, which may allow for improved jitter tolerance and reduced bit error rate.

Abstract: The present invention is directed to a method which allows for substitution of standard SAS ALIGN primitives with an alternative, more spectrally pure set of SAS ALIGN primitives that allows for enhanced continuous adaptation performance. Two consenting SAS devices which are connected to each other may negotiate for and start communicating using the alternate set of ALIGN primitives, which may allow for improved jitter tolerance and reduced bit error rate.

Abstract: The present invention is directed to a system and method for emulating a serial small computer system interface (SAS) connection for direct attached serial advanced technology attachment (SATA) communication are disclosed. A system in accordance with the present invention includes a host controller. The host controller includes a physical interface for accepting at least one of a SAS connection or a direct attached SATA device. A common interface logic configured to receive SAS communications and SATA communications having a SAS emulated connection is included in the host controller. An emulation logic is communicatively coupled to the common interface logic. The emulation logic being configured to determine a value of a ConnectedSata signal based on the state of a SATA link state machine.

Abstract: Methods and associated structure to assure correct order in delivery of SATA frames over a SAS wide port. In one aspect hereof, new connection requests from a SATA device are rejected until prior frames residing in receive buffers of the SAS/SATA controller are properly processed. In another aspect, when a device is already connected to the controller, the SAS/SATA controller may prevent return of a receiver ready primitive in response to a transmitter ready primitive until previously received frames are removed from the receive buffers.

Abstract: Apparatus and associated methods for a simplified Serial SCSI Protocol (“SSP”) link layer within a SAS device. Features and aspects hereof provide a simplified SSP link layer processor to enable cost reduction and simplification of Serial Attached SCSI (“SAS”) devices requiring only limited SSP exchange functionality. In one embodiment, a SAS expander may incorporate the simplified SSP link layer features and aspects hereof to permit simple management of SAS devices coupled to the expander or coupled downstream through other expanders. The simplified SSP link layer suffices for simple SAS management functions while reducing cost and complexity of the SAS expander. Features and aspects hereof may be implemented with minimal customized circuits for SSP link layer management in the SAS device. In one aspect hereof, the simplified link layer processing may be implemented as a simplified state machine model in combinatorial logic coupled with any requisite memory components.

Abstract: Methods and structures for efficiently storing task file information for a significant number of SATA devices coupled to a SATA storage controller. A RAM memory within the SATA storage controller may store task file information for virtually any number of SATA devices coupled to a SAS communication domain. An arbiter and multiplexing logic is coupled to multiple client logic blocks or processes of the controller each operable to control one or more corresponding SATA devices. The arbiter and associated multiplexing logic grants each client process an opportunity to control its corresponding devices by retrieving saved state information from the task file RAM storage.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for a Serial ATA interface that utilizes a combination of IOP control and specialized hardware control. The method may include steps as follows. It is determined, preferably based on a value of the Automate bit in a Task File Ram of a Serial ATA interface, whether a Serial ATA device of the Serial ATA interface is being controlled via the IOP or controlled by the specialized Serial ATA automation hardware. When the Serial ATA device is controlled via the IOP, the IOP may decide when to power up/down the Serial ATA interface. When the Serial ATA device is controlled by the specialized Serial ATA automation hardware, the method may proceed as follows. An idle or active condition of a Serial ATA interface utilizing a combination of IOP control and specialized hardware control is then automatically detected.

Abstract: Disclosed is a system using a SAS host controller and SAS expanders to control multiple SATA end devices where the memory contained on the SAS host controller is fixed to ease the cost and power consumption of the SAS host controller device, but where there is an expanded ability to support additional SATA end devices by configuring the allowed native command queue depth to be smaller for each SATA end device, thus allowing more SATA end devices to be supported by a single SAS host controller. An embodiment of the invention has three possible preset configuration states: thirty-two SATA end devices with a native command queue depth of thirty-two; sixty-four SATA end devices with a native command queue depth of sixteen; and one-hundred-twenty-eight SATA end devices with a native command queue depth of eight.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for a Serial ATA device directly attached to a SAS/SATA host controller. In an exemplary aspect of the present invention, it is determined whether a Serial ATA device is directly attached to a SAS/SATA host controller without using a SAS expander. When it is determined that the Serial ATA device is directly attached to the SAS/SATA host controller, an idle or active condition of a Serial ATA interface including the Serial ATA device and the SAS/SATA host controller is automatically detected. When the Serial ATA interface is in an idle condition, idle time of the Serial ATA interface is measured using a power down counter whose frequency is determined by a programmable register based on an input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for Serial ATA interface. In an exemplary aspect of the present invention, an idle or active condition of a Serial ATA interface including a NCQ Serial ATA device is automatically detected. In this step, it is determined, preferably based on a value of the FPDMA (First Party Direct Memory Access) bit in a Task File Ram of the Serial ATA interface, whether the NCQ Serial ATA device is in a FPDMA Data Phase. When the NCQ Serial ATA device is in a FPDMA Data Phase, the Serial ATA interface is active (i.e., not idle). When Serial ATA is in an idle condition, idle time of Serial ATA interface is measured using a power down counter whose frequency is determined by a programmable register based on an input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for Serial ATA interface. In an exemplary aspect of the present invention, an idle or active condition of a Serial ATA interface including a NCQ Serial ATA device is automatically detected. In this step, it is determined, preferably based on a value of the FPDMA (First Party Direct Memory Access) bit in a Task File Ram of the Serial ATA interface, whether the NCQ Serial ATA device is in a FPDMA Data Phase. When the NCQ Serial ATA device is in a FPDMA Data Phase, the Serial ATA interface is active (i.e., not idle). When Serial ATA is in an idle condition, idle time of Serial ATA interface is measured using a power down counter whose frequency is determined by a programmable register based on an input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state.

Abstract: The present invention provides bridge device for transferring data using master-specific prefetch sizes. The bridge device is coupled between a first bus and a second bus with the master devices being coupled to the first bus and the slave devices being coupled to the second bus. The bridge device includes a set of prefetch control registers, a prefetch buffer, and bridge control circuitry. The set of prefetch control registers is arranged to store prefetch sizes of data to be prefetched for a set of the master devices with one prefetch control register being provided for a master device. The prefetch buffer is arranged to store data for transfer. The bridge control circuitry is coupled to the prefetch control registers and the prefetch buffer for transferring data between a source device and a destination device.

Abstract: The present invention provides a bridge device and a method for generating message signaled interrupts to indicate completion of write transactions from one or more secondary bus devices to a primary bus device. The bridge device is coupled between a first bus and a second bus. The one or more secondary bus devices are coupled to the second bus and the primary bus device is coupled to the first bus. The bridge device includes a bridge FIFO and control circuitry, a first register, and an interrupt generation logic. The bridge FIFO and control circuitry is arranged to control data transfer between the one or more secondary bus devices and the primary bus device. The bridge FIFO and control circuitry is further configured to store and transfer write data from the one or more secondary bus devices to the primary bus device. The first register is arranged to store a set of interrupt bit numbers.

Abstract: The present invention provides a RAID controller coupled to a host computer system through a primary PCI bus. The RAID controller includes a PCI application bridge, a RAID processor and chipset, and an expansion ROM. The PCI application bridge is coupled to interface data and command transfers between the primary PCI bus and a secondary PCI bus. The RAID processor and chipset is coupled to said secondary PCI bus for controlling access to said one or more RAID arrays. The expansion ROM is configured to store device specific codes and BIOS codes for initializing said RAID controller and said host computer system for boot-up. For initializing said RAID controller, the said RAID processor and chipset accesses said device specific codes in said expansion ROM. The RAID processor and chipset provides a first address corresponding to said BIOS codes in said expansion ROM to said PCI bus application bridge.

Abstract: A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells of all types, and the interaction of external pull cells/resistors with pad cells of all types. This modeling technique involves the use of three separate pins on each bi-directional pad cell: an input-only pin, an output-only pin, and a resolved pin. The input-only pin reflects the data that is supplied to the pad from external sources. The output-only pin reflects the data that is supplied as output from the pad cell (strong data from the output driver). The resolved pin reflects the combination of the input and the output data that are present, as well as the effect of resistive data supplied by pull-up/down resistors/cells. The output-only and resolved pins are implemented as internal or hidden pins within a pad cell model. These pins are included in the model for the I/O pad cells in a given library. The existing pad pin serves as the input-only pin.

Abstract: A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells of all types, and the interaction of external pull cells/resistors with pad cells of all types. This modeling technique involves the use of three separate pins on each bi-directional pad cell: an input-only pin, an output-only pin, and a resolved pin. The input-only pin reflects the data that is supplied to the pad from external sources. The output-only pin reflects the data that is supplied as output from the pad cell (strong data from the output driver). The resolved pin reflects the combination of the input and the output data that are present, as well as the effect of resistive data supplied by pull-up/down resistors/cells. The output-only and resolved pins are implemented as internal or hidden pins within a pad cell model. These pins are included in the model for the I/O pad cells in a given library. The existing pad pin serves as the input-only pin.