Patents by Inventor Patrick R. Brown
Patrick R. Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250036112Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for optimizing a process of manufacturing a product. In one aspect, the method comprises repeatedly performing the following: i) selecting a configuration of input settings for manufacturing a product, based on a causal model that measures causal relationships between input settings and a measure of a quality of the product; ii) determining the measure of the quality of the product manufactured using the configuration of input settings; and iii) adjusting, based on the measure of the quality of the product manufactured using the configuration of input settings, the causal model.Type: ApplicationFiled: October 16, 2024Publication date: January 30, 2025Inventors: Brian E. Brooks, Gilles J. Benoit, Peter O. Olson, Tyler W. Olson, Himanshu Nayar, Frederick J. Arsenault, Nicholas A. Johnson, Brett R. Hemes, Thomas J. Strey, Jonathan B. Arthur, Nathan J. Herbst, Aaron K. Nienaber, Sarah M. Mullins, Mark W. Orlando, Cory D. Sauer, Timothy J. Clemens, Scott L. Barnett, Zachary M. Schaeffer, Patrick G. Zimmerman, Gregory P. Moriarty, Jeffrey P. Adolf, Steven P. Floeder, Andreas Backes, Peter J. Schneider, Maureen A. Kavanagh, Glenn E. Casner, Miaoding Dai, Christopher M. Brown, Lori A. Sjolund, Jon A. Kirschhoffer, Carter C. Hughes
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Patent number: 10680194Abstract: A light emitting device can include a light source, a first electrode, a second electrode, a first barrier layer, a second barrier layer, and an emitter layer between the first barrier layer and the second barrier layer. A method of controllably generating light can comprise two states: An ON state, wherein an emitter layer of a device (which includes a photoluminescent pixel) is illuminated with a light source in the absence of an electric field, and the emitter layer generates light through photoluminescence; and an OFF state, wherein an emitter layer of a device (which includes a photoluminescent pixel) is illuminated with a light source in the presence of a static or time-varying electric field, and the electric field or induced current results in quenching of the emitter photoluminescence.Type: GrantFiled: January 12, 2016Date of Patent: June 9, 2020Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Patrick R. Brown, Geoffrey J. Supran, Jeffrey C. Grossman, Moungi G. Bawendi, Vladimir Bulovic
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Patent number: 10453168Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: GrantFiled: August 17, 2018Date of Patent: October 22, 2019Assignee: NVIDIA CORPORATIONInventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
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Patent number: 10169072Abstract: A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first thread of the plurality of parallel threads to be executed by a processing unit; and causing a second command list associated with a second thread of the plurality of parallel threads to be executed by the processing unit, where the second command list inherits from the first command list state associated with the processing unit.Type: GrantFiled: August 9, 2010Date of Patent: January 1, 2019Assignee: NVIDIA CORPORATIONInventors: Jerome F. Duluk, Jr., Jesse David Hall, Henry Packard Moreton, Patrick R. Brown
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Publication number: 20180374185Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: ApplicationFiled: August 17, 2018Publication date: December 27, 2018Inventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
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Patent number: 10134169Abstract: One embodiment of the present invention sets forth a method for accessing texture objects stored within a texture memory. The method comprises the steps of receiving a texture bind request from an application program, wherein the texture bind request includes an object identifier that identifies a first texture object stored in the texture memory and an image identifier that identifies a first image unit, binding the first texture object to the first image unit based on the texture bind request, receiving, within a shader engine, a first shading program command from the application program for performing a first memory access operation on the first texture object, wherein the memory access operation is a store operation or atomic operation to an arbitrary location in the image, and performing, within the shader engine, the first memory access operation on the first texture object via the first image unit.Type: GrantFiled: August 12, 2010Date of Patent: November 20, 2018Assignee: NVIDIA CORPORATIONInventors: Jeffrey A. Bolz, Patrick R. Brown
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Patent number: 10055806Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: GrantFiled: October 27, 2015Date of Patent: August 21, 2018Assignee: NVIDIA CORPORATIONInventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
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Patent number: 10032245Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: GrantFiled: October 27, 2015Date of Patent: July 24, 2018Assignee: NVIDIA CORPORATIONInventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
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Patent number: 10019776Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: GrantFiled: October 27, 2015Date of Patent: July 10, 2018Assignee: NVIDIA CORPORATIONInventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
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Publication number: 20170271604Abstract: A method of improving performance of a photovoltaic device can include modifying a surface energy level of a nanocrystal through ligand exchange. A photovoltaic device can include a layer that includes a nanocrystal with a surface energy modified through ligand exchange.Type: ApplicationFiled: May 8, 2015Publication date: September 21, 2017Applicant: Massachusetts Institute of TechnologyInventors: Patrick R. Brown, Donghun KIM, Moungi G. Bawendi, Jeffrey C. Grossman, Vladimir Bulovic
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Patent number: 9754561Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.Type: GrantFiled: October 4, 2013Date of Patent: September 5, 2017Assignee: NVIDIA CORPORATIONInventors: Jonathan Dunaisky, Henry Packard Moreton, Jeffrey A. Bolz, Yury Y. Uralsky, James Leroy Deming, Rui M. Bastos, Patrick R. Brown, Amanpreet Grewal, Christian Amsinck, Poornachandra Rao, Jerome F. Duluk, Jr., Andrew J. Tao
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Patent number: 9665958Abstract: A system, method, and computer program product are provided for redistributing multi-sample processing workloads between threads. A workload for a plurality of multi-sample pixels is received and each thread in a parallel thread group is associated with a corresponding multi-sample pixel of the plurality of pixels. The workload is redistributed between the threads in the parallel thread group based on a characteristic of the workload and the workload is processed by the parallel thread group. In one embodiment, the characteristic is rasterized coverage information for the plurality of multi-sample pixels.Type: GrantFiled: August 26, 2013Date of Patent: May 30, 2017Assignee: NVIDIA CorporationInventors: Jeffrey Alan Bolz, Patrick R. Brown, Tyson Bergland, Alexander Lev Minkin
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Publication number: 20170116698Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: ApplicationFiled: October 27, 2015Publication date: April 27, 2017Inventors: ZIYAD HAKURA, ERIC LUM, DALE KIRKLAND, JACK CHOQUETTE, PATRICK R. BROWN, YURY Y. URALSKY, JEFFREY BOLZ
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Publication number: 20170116699Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: ApplicationFiled: October 27, 2015Publication date: April 27, 2017Inventors: ZIYAD HAKURA, ERIC LUM, DALE KIRKLAND, JACK CHOQUETTE, PATRICK R. BROWN, YURY Y. URALSKY, JEFFREY BOLZ
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Publication number: 20170116700Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: ApplicationFiled: October 27, 2015Publication date: April 27, 2017Inventors: ZIYAD HAKURA, ERIC LUM, DALE KIRKLAND, JACK CHOQUETTE, PATRICK R. BROWN, YURY Y. URALSKY, JEFFREY BOLZ
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Patent number: 9589310Abstract: One embodiment of the present invention sets forth a technique for splitting a set of vertices into a plurality of batches for processing. The method includes receiving one or more primitives each containing an associated set of vertices. For each of the one or more primitives, one or more vertices are gathered from the set of vertices, the vertices are arranged into one or more batches, the batch is routed to a processing pipeline line to process each batch as a separate primitive, and the one or more batches are processed to produce results identical to those of processing the entire primitive as a single entity.Type: GrantFiled: October 5, 2010Date of Patent: March 7, 2017Assignee: NVIDIA CorporationInventors: Jerome F. Duluk, Jr., Thomas Roell, Patrick R. Brown
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Patent number: 9448935Abstract: Techniques are disclosed for performing memory access operations. A texture unit receives a memory access operation that includes a tuple associated with a first view in a plurality of views. The texture unit retrieves a first hash value associated with a first texture header in a plurality of texture headers, where the first texture header is related to the first view. The texture unit retrieves a second hash value associated with a second texture header in the plurality of texture headers, where the second texture header is related to a second view. The texture unit determines whether the first view is potentially aliased with the second view, based on the first and second hash values. If so, then the texture unit invalidates a cache entry in a cache memory associated with the second texture header. Otherwise, the texture unit maintains the cache entry.Type: GrantFiled: September 25, 2013Date of Patent: September 20, 2016Assignee: NVIDIA CorporationInventors: Jeff Bolz, Patrick R. Brown, Steven J. Heinrich, Dale L. Kirkland, Joel McCormack
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Patent number: 9436971Abstract: A system, method, and computer program product are provided for accessing multi-sample surfaces. A multi-sample store instruction that specifies data for a single sample of a multi-sample pixel and a sample mask is received and the data for the single sample is stored to each sample of the multi-sample pixel that is enabled according to the sample mask. A multi-sample load instruction that specifies a multi-sample pixel is received, and, in response to executing the multi-sample load instruction, data for one sample of the multi-sample pixel is received. A determination is made that the data for the one sample of the multi-sample pixel represents multi-sample pixel data for at least one additional sample of the multi-sample pixel.Type: GrantFiled: August 19, 2013Date of Patent: September 6, 2016Assignee: NVIDIA CorporationInventors: Jeffrey Alan Bolz, Patrick R. Brown, Tyson Bergland, Alexander Lev Minkin
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Patent number: 9401004Abstract: One embodiment of the present invention sets forth a technique for tracking and filtering state change methods provided to a graphics pipeline. State shadow circuitry at the start of the graphics pipeline may be configured in different modes. A track mode is used to capture the current state by storing state change methods that are transmitted to the graphics pipeline. A passthrough mode is used to provide different state data to the graphics pipeline without updating the current state stored in the state shadow circuitry. A replay mode is used to restore the current state to the graphics pipeline using the state shadow circuitry. Additionally, the state shadow circuitry may also be configured to filter the state change methods that are transmitted to graphics pipeline by removing redundant state change methods.Type: GrantFiled: October 12, 2010Date of Patent: July 26, 2016Assignee: NVIDIA CorporationInventors: Jerome Francis Duluk, Jr., Jesse David Hall, Patrick R. Brown, Gregory Scott Palmer, Eric S. Werness
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Publication number: 20160201881Abstract: A light emitting device can include a light source, a first electrode, a second electrode, a first barrier layer, a second barrier layer, and an emitter layer between the first barrier layer and the second barrier layer. A method of controllably generating light can comprise two states: An ON state, wherein an emitter layer of a device (which includes a photoluminescent pixel) is illuminated with a light source in the absence of an electric field, and the emitter layer generates light through photoluminescence; and an OFF state, wherein an emitter layer of a device (which includes a photoluminescent pixel) is illuminated with a light source in the presence of a static or time-varying electric field, and the electric field or induced current results in quenching of the emitter photoluminescence.Type: ApplicationFiled: January 12, 2016Publication date: July 14, 2016Applicant: Massachusetts Institute of TechnologyInventors: Patrick R. Brown, Geoffrey J. Supran, Jeffrey C. Grossman, Moungi G. Bawendi, Vladimir Bulovic