Patents by Inventor Patrick R. Hansen
Patrick R. Hansen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6731179Abstract: A ring oscillator (and test circuit incorporating the ring oscillator and test method therefor) includes an odd number of elements interconnected in a serially-connected infinite loop, each oscillator element having an associated programmable delay feature. The circuit can be used to measure effects of Negative Bias Temperature Instability (NBTI) in p-channel MOSFETs (PFETs).Type: GrantFiled: April 9, 2002Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventors: Wagdi William Abadeer, Wayne Frederick Ellis, Patrick R. Hansen, Jonathan M. McKenna
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Publication number: 20030189465Abstract: A ring oscillator (and test circuit incorporating the ring oscillator and test method therefor) includes an odd number of elements interconnected in a serially-connected infinite loop, each oscillator element having an associated programmable delay feature. The circuit can be used to measure effects of Negative Bias Temperature Instability (NBTI) in p-channel MOSFETs (PFETs).Type: ApplicationFiled: April 9, 2002Publication date: October 9, 2003Applicant: International Business Machines CorporationInventors: Wagdi William Abadeer, Wayne Frederick Ellis, Patrick R. Hansen, Jonathan M. McKenna
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Patent number: 6617986Abstract: A Sequential Gray Code to Thermometer Code decoder circuit adapted for area efficient use at each pad of an integrated circuit chip for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations. The sequential decoder for decoding a Gray code count to a T-bit Thermometer code count is constructed of a plurality (T) of cascaded decoder cells, each cell sensing the state of only one bit of the Gray code count. The decoder cells are cascaded to from decoding-latching stages each stage responsive to an individual one of single-bit changes between consecutive counts in the Gray code. Each stage contains a decoding-latching circuit adapted to detecting and latching the occurrence of one single-bit change in the Gray code.Type: GrantFiled: September 4, 2001Date of Patent: September 9, 2003Assignee: International Business Machines CorporationInventors: John Connor, Patrick R. Hansen, Steven Leschuk, Jason E. Rotella
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Publication number: 20030071747Abstract: A Sequential Gray Code to Thermometer Code decoder circuit adapted for area efficient use at each pad of an integrated circuit chip for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations. The sequential decoder for decoding a Gray code count to a T-bit Thermometer code count is constructed of a plurality (T) of cascaded decoder cells, each cell sensing the state of only one bit of the Gray code count. The decoder cells are cascaded to from decoding-latching stages each stage responsive to an individual one of single-bit changes between consecutive counts in the Gray code. Each stage contains a decoding-latching circuit adapted to detecting and latching the occurrence of one single-bit change in the Gray code.Type: ApplicationFiled: September 4, 2001Publication date: April 17, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Connor, Patrick R. Hansen, Steven Leschuk, Jason E. Rotella
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Patent number: 6542418Abstract: An integrated circuit memory structure includes a main array of memory elements having wordlines and bitlines and a redundant array of redundant memory elements external to and connected to the main array. Each of the redundant memory elements can replace either one of the wordlines or one of the bitlines.Type: GrantFiled: June 26, 2001Date of Patent: April 1, 2003Assignee: International Business Machines CorporationInventors: George M. Braceras, Patrick R. Hansen
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Patent number: 6509778Abstract: Disclosed is a programmable impedance driver that includes two sets of impedance devices, two primary counters and two test counters. The primary counters selectively activate individual ones of the impedance devices to vary an overall impedance of the driver and the test counters verify the counting operation of the primary counters during manufacturing testing of the driver. Therefore, the built-in self-test (BIST) aspect of the invention easily detects if one of the counters will become stuck during normal usage.Type: GrantFiled: March 15, 2001Date of Patent: January 21, 2003Assignee: International Business Machines CorporationInventors: George M Braceras, Steven Burns, Patrick R. Hansen, Harold Pilo
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Patent number: 6501293Abstract: A method and apparatus for providing programmable active termination of transmission lines with substantially reduced DC power consumption.Type: GrantFiled: November 12, 1999Date of Patent: December 31, 2002Assignee: International Business Machines CorporationInventors: George M. Braceras, John Connor, Patrick R. Hansen
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Publication number: 20020196677Abstract: An integrated circuit memory structure includes a main array of memory elements having wordlines and bitlines and a redundant array of redundant memory elements external to and connected to the main array. Each of the redundant memory elements can replace either one of the wordlines or one of the bitlines.Type: ApplicationFiled: June 26, 2001Publication date: December 26, 2002Applicant: International Business Machines CorporationInventors: George M. Braceras, Patrick R. Hansen
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Publication number: 20020130697Abstract: Disclosed is a programmable impedance driver that includes two sets of impedance devices, two primary counters and two test counters. The primary counters selectively activate individual ones of the impedance devices to vary an overall impedance of the driver and the test counters verify the counting operation of the primary counters during manufacturing testing of the driver. Therefore, the built-in self-test (BIST) aspect of the invention easily detects if one of the counters will become stuck during normal usage.Type: ApplicationFiled: March 15, 2001Publication date: September 19, 2002Applicant: International Business Machines CorporationInventors: George M. Braceras, Steven Burns, Patrick R. Hansen, Harold Pilo
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Patent number: 6441646Abstract: A structure and method for reducing bipolar current in of a SOI circuit by alternating precharge low and precharge high methodologies comprises a reset signal source coupled to an inverter and a primary node, further coupled to a first and second PFET device; a clock signal source; coupled to a first NFET device and a third PFET device; a first input signal source coupled to a second NFET device and a fourth PFET device; a first NFET stack node coupled to the third PFET device, the first NFET device, the primary node, and the second NFET device; a second input signal source coupled to a third NFET device; a fifth PFET device coupled to the fourth PFET device; a power supply voltage source coupled to the fifth PFET device; and a second NFET node coupled to the fourth PFET device, the second NFET device, and the third NFET device.Type: GrantFiled: October 31, 2001Date of Patent: August 27, 2002Assignee: International Business Machines CorporationInventors: George M. Braceras, Patrick R. Hansen
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Publication number: 20020005734Abstract: A method and apparatus for providing programmable active termination of transmission lines with substantially reduced DC power consumption.Type: ApplicationFiled: November 12, 1999Publication date: January 17, 2002Inventors: GEORGE M. BRACERAS, JOHN CONNOR, PATRICK R. HANSEN
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Patent number: 6278339Abstract: An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit.Type: GrantFiled: December 13, 2000Date of Patent: August 21, 2001Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, John Connor, Patrick R. Hansen
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Patent number: 6269461Abstract: A testing device for slowly bleeding charge away from a primary node in a dynamic logic circuit. A properly functioning keeper device in the dynamic logic circuit will maintain the primary node in a precharged state even in the face of this bleeding device. If the logic circuit output flips after the bleeder device begins bleeding charge, a defective keeper device is thereby identified.Type: GrantFiled: April 27, 1998Date of Patent: July 31, 2001Assignee: International Business Machines CorporationInventors: Robert Dean Adams, Patrick R. Hansen, Phillip Nigh
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Patent number: 6249193Abstract: An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit.Type: GrantFiled: May 27, 1999Date of Patent: June 19, 2001Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, John Connor, Patrick R. Hansen
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Publication number: 20010000428Abstract: An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit.Type: ApplicationFiled: December 13, 2000Publication date: April 26, 2001Inventors: Wagdi W. Abadeer, John Connor, Patrick R. Hansen
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Patent number: 6181155Abstract: A method and apparatus for detecting whether dynamic logic circuits are precharging properly. The method and apparatus uses a narrowed reset pulse to verify precharging is occurring as designed.Type: GrantFiled: April 28, 1999Date of Patent: January 30, 2001Assignee: International Business Machines CorporationInventors: R. Dean Adams, Patrick R. Hansen
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Patent number: 6163862Abstract: An on-chip test circuit for evaluating on-chip signals for a semiconductor memory chip includes an on-chip signal associated with a memory circuit on the chip; said on-chip signal having a signal characteristic to be evaluated; an input circuit for receiving an off-chip test signal; and a test circuit that compares said on-chip signal and said test signal.Type: GrantFiled: December 1, 1997Date of Patent: December 19, 2000Assignee: International Business Machines CorporationInventors: R. Dean Adams, Edmond S. Cooley, Patrick R. Hansen
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Patent number: 6140885Abstract: An impedance matching system and a network for automatic impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises a control circuit which varies a control voltage proportionally to the frequency of voltage transients that occur on the driver circuit output, an adjustment mechanism which provides a linear motion proportional to the control voltage, and an adjustable length transmission line whose length is adjusted in proportion to the frequency of voltage transients on the driver circuit output and whose impedance, which is purely reactive, is proportional to its length. The purpose of the adjustable length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver network to the driver circuit. In the preferred embodiment, the impedance matching network is manufactured on the same chip as the driver circuit.Type: GrantFiled: February 23, 1999Date of Patent: October 31, 2000Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, John Connor, Patrick R. Hansen
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Patent number: 6133749Abstract: A programmable variable impedance output driver circuit uses analog biases to match driver output impedance to load input impedance. A current mirror is used to obtain a measurement of an external resistance value for matching the impedance of a driven load. The mirrored current generates the voltage "NBIAS" when passed through the resistively connected NFET. Similarly, the current is again mirrored and passed through a resistively connected PFET resulting in the voltage "PBIAS". The analog bias voltages, NBIAS and PBIAS are used to vary the impedance of complementary FETs in an impedance matched driver for a high degree of dI/dt control. The driver provides a high degree of flexibility because its turn-on and turn-off characteristics do not depend on a combination of digital control signals connected directly to the driving FETs as in the prior art.Type: GrantFiled: January 4, 1999Date of Patent: October 17, 2000Assignee: International Business Machines CorporationInventors: Patrick R. Hansen, Harold Pilo