Abstract: Methods, systems, and apparatuses include detecting a failure to decode a first codeword, the first codeword including user data and first level parity data for the user data. A second codeword is read in response to the detected failure, the second codeword including second level parity data for the user data. A first set of one or more reliability values is selected for the second level parity data, the first set of reliability values differing from a second set of reliability values for the user data and the first level parity data. The user data is decoded using the first level parity data, the second level parity data, the selected first set of reliability values, and the second set of reliability values.

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including reading a first copy of data stored in a first set of memory cells comprising a first memory cell, determining whether a threshold voltage of the first memory cell is within a first range of threshold voltages, responsive to determining that the threshold voltage of the first memory cell is within the first range of threshold voltages, reading a second copy of the data stored in a second set of memory cells comprising a second memory cell, determining whether a threshold voltage of the second memory cell is within a second range of threshold voltages, and responsive to determining that the threshold voltage of the second memory cell is outside the second range, using the second copy of the data.

Abstract: A processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. Responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.

Abstract: A processing device in a memory sub-system monitors a temperature associated with a block of a memory device, the block comprising a plurality of wordlines. The processing device further determines a first amount of time between when memory cells associated with a first wordline of the plurality of wordlines of the block were written and when memory cells associated with a last wordline of the plurality of wordlines of the block were written. That first amount of time is normalized according to the temperature associated with the block. The processing device further determines, based at last in part on the first amount of time and on an associated scaling factor, an estimate of when the block will reach a uniform charge loss state.

Abstract: A system comprising a memory device comprising a plurality of memory cells and a processing device, operatively coupled with the memory device, to perform operations. The processing device determines, for each memory cell of the plurality of memory cells, a respective value of a metric that reflects a sensitivity of a threshold voltage of the memory cell to a change in an adjacent memory cell. The processing device determines, for each wordline of a plurality of wordlines of the memory device, based on the determined values of the metric, a respective aggregate measure of adjacent cell dependence. The processing device categorizes the wordlines into one or more wordline groups based on comparing, for each wordline, the determined aggregate measure of adjacent cell dependence to at least one threshold dependence value.

Abstract: A processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. Responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.

Abstract: Embodiments disclosed can include determining, for each memory cell connected to each wordline, a respective value of a metric that reflects a sensitivity of a threshold voltage associated with the memory cell to a change in a threshold voltage of an adjacent cell and determining, for each wordline, based on the determined sensitivity for each memory cell, a respective aggregate measure of adjacent cell dependence. They can further include comparing the determined aggregate measure of adjacent cell dependence to a threshold dependence value. They can also include identifying a first wordline group having wordlines with high adjacent cell dependence and a second wordline group having wordlines with low adjacent cell dependence and storing a record referencing the wordlines of the second wordline group, the record indicating a corresponding location on the die of the memory device.

Abstract: A system includes a memory device; and a processing device, operatively coupled to the memory device, the processing device to perform operations including: receiving a request to perform a read operation, the request identifying a set of memory cells in a portion of a memory device; determining a first temperature of the set of memory cells, wherein the first temperature is associated with a first error handing operation of an error handling flow directed to the set of memory cells; determining an offset value to be applied to a temperature compensation coefficient of a parameter of a set of parameters associated with the set of memory cells, wherein the offset value is associated with a temperature range comprising the first temperature; determining a second temperature of the set of memory cells, wherein the second temperature is associated with a second error handling operation following the first error handing operation of the error handling flow directed to the set of memory cells; and responsive to det

Abstract: A memory device includes array(s) of memory cells including first memory cells configured as single-level cell memory and second memory cells configured as higher-level cell memory. Page buffer(s) are coupled with the array(s). Logic is coupled with the page buffer(s) and to cause, in response to receipt of a copyback clear command, a page buffer to perform a dual-strobe read operation on the first memory cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage. The logic causes the page buffer to determine a number of one bit values within a threshold voltage range between the first threshold voltage and the second threshold voltage. The logic causes, responsive to the number of one bit values not satisfying a threshold criterion, a copyback be performed of data in the first memory cells to the second memory cells.

Abstract: Embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a respective value of a sensitivity metric that reflects a sensitivity of a threshold voltage of a memory cell associated with the wordline to a change in a threshold voltage of an adjacent memory cell. Embodiments can also include determining, for the wordline, that the respective value of the sensitivity metric satisfies a threshold criterion. Embodiments can further include responsive to determining that the respective value of the sensitivity metric satisfies the threshold criterion, associating the wordline with a first wordline group, wherein the first wordline group comprises one or more wordlines, and wherein each wordline of the one or more wordlines is associated with a respective value of the sensitivity metric that satisfies the threshold criterion. Embodiments can include performing, on a specified memory cell connected to the wordline associated with the first wordline group, a compensatory operation.

Abstract: Processing logic in a memory device receives a calibration scan command associated with the memory device. In response to the calibration scan command, execution of a set of read operations at a plurality of read voltage levels on the memory device is caused. In response to the calibration scan command, a set of bit counts is identified, where each bit count of the set of bit counts corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels. Based on the bit count corresponding to each bin of the set of bins, a bin having a lowest bit count is identified.

Abstract: Embodiments disclosed can include determining, for each wordline group of one or more wordline groups of the plurality of wordlines, a target adjustment to a parameter of a memory access operation that is performed with respect to a memory cell associated with a wordline of the wordline group; and responsive to determining that an aggregate read window budget (RWB) increase for the block satisfies a threshold range associated with a target RWB increase, modifying the parameter of the memory access operation according to the target adjustment, wherein the target RWB increase is determined using a different PV voltage offset for each respective programming level of the memory cell associated with the wordline of the wordline group.

Abstract: A system having a processing device operatively coupled with a memory device to perform the following operations: responsive to detecting a triggering event, measuring a temperature of the memory device to obtain a suspend temperature value, enabling a suspend temperature flag to indicate that temperature input for a step of an error handling operation is based on the suspend temperature value. Updating an operating temperature with the suspend temperature value. Determining, using a data structure which maps temperatures to read level offsets, a read level offset for the step of the error handling operation, based on the operating temperature. Causing the step of the error handling operation to be performed on a set of cells using a read level value based on the read level offset and a base read level, an disabling the suspend temperature flag.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising initiating a copyback operation to copy data from a first set of memory cells of the memory device to a second set of memory cells of the memory device; responsive to receiving a read command associated with a third set of memory cells configured to store a predefined number of bits per memory cell, suspending performing the copyback operation; performing a data integrity check on a subset of the third set of memory cells to obtain a data integrity metric value; responsive to determining that the data integrity metric value satisfies a threshold criterion, performing an error-handling operation on data stored on the third set of memory cells; and resuming performing the copyback operation.

Abstract: Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.

Abstract: Embodiments disclosed can include identifying wordline groups where each wordline group is associated with a corresponding default program verify (PV) voltage for each programming level, and determining, for each wordline group, a maximum read window budget (RWB) increase. They can further include defining a target aggregate RWB increase amount based on the maximum RWB increase, and determining, for each wordline group, a minimum number of memory cell programming level groups with corresponding PV voltage offsets sufficient to reach the target aggregate RWB increase amount. The embodiments can also include grouping the programming levels of a specified memory cell into the minimum number of programming level, and applying, based on the specific programming level group containing a target programming level, a corresponding PV voltage offset during a memory cell access operation.

Abstract: Embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a respective value of a sensitivity metric that reflects a sensitivity of a threshold voltage of a memory cell associated with the wordline to a change in a threshold voltage of an adjacent memory cell. Embodiments can also include determining, for the wordline, that the respective value of the sensitivity metric satisfies a threshold criterion. Embodiments can further include responsive to determining that the respective value of the sensitivity metric satisfies the threshold criterion, associating the wordline with a first wordline group, wherein the first wordline group comprises one or more wordlines, and wherein each wordline of the one or more wordlines is associated with a respective value of the sensitivity metric that satisfies the threshold criterion. Embodiments can include performing, on a specified memory cell connected to the wordline associated with the first wordline group, a compensatory operation.

Abstract: Embodiments disclosed can include selecting a target read window budget (RWB) increase and identifying a set of aggressor memory cells. They can also include generating a list of programming level states for the set of aggressor memory cells and identifying, in the list, an entry associated with a maximum RWB increase that is greater than or equal to the target RWB increase. They can further include responsive to identifying the entry with the total number of bits associated with a maximum RWB increase that is greater than or equal to the target RWB increase, modifying a parameter of the memory access operation with the adjustment associated with the identified entry.

Abstract: A method includes receiving, by control logic of a memory device, a copyback clear command from a processing device; causing, in response to the copyback clear command, a page buffer to perform a dual-strobe read operation on first memory cells configured as single-level cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage that are sensed between threshold voltage distributions of the first memory cells; causing the page buffer to determine a number of one bit values within the threshold voltage distributions detected in a threshold voltage range between the first/second threshold voltages; and causing, in response to the number of one bit values not satisfying a threshold criterion, a copyback of data in the first memory cells to second memory cells configured as high-level cells without intervention from the processing device.

Abstract: Embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a target read window budget (RWB) increase, wherein the target RWB increase corresponds to a maximum RWB increase associated with using a different PV voltage offset for each respective programming level of a memory cell. Embodiments can also include segmenting the plurality of wordlines into one or more wordline groups, wherein each wordline group comprises one or more wordlines. Embodiments can further include determining, for each wordline group, a target adjustment to a parameter of a memory access operation that is performed with respect to a memory cell associated with a wordline of the wordline group. Embodiments can include determining an aggregate RWB increase for the block in view of the target adjustment to the parameter of the memory access operation.