Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including reading a first copy of data stored in a first set of memory cells comprising a first memory cell, determining whether a threshold voltage of the first memory cell is within a first range of threshold voltages, responsive to determining that the threshold voltage of the first memory cell is within the first range of threshold voltages, reading a second copy of the data stored in a second set of memory cells comprising a second memory cell, determining whether a threshold voltage of the second memory cell is within a second range of threshold voltages, and responsive to determining that the threshold voltage of the second memory cell is outside the second range, using the second copy of the data.

Abstract: A processing device in a memory sub-system monitors a temperature associated with a block of a memory device, the block comprising a plurality of wordlines. The processing device further determines a first amount of time between when memory cells associated with a first wordline of the plurality of wordlines of the block were written and when memory cells associated with a last wordline of the plurality of wordlines of the block were written. That first amount of time is normalized according to the temperature associated with the block. The processing device further determines, based at last in part on the first amount of time and on an associated scaling factor, an estimate of when the block will reach a uniform charge loss state.

Abstract: Described are memory devices producing metadata characterizing the applied read voltage level with respect to voltage distributions. An example memory sub-system comprises: a memory device comprising a plurality of memory cells; and a controller coupled to the memory device, the controller to perform operations comprising: performing, using a read voltage level, a read strobe with respect to a subset of the plurality of memory cells; and receiving, from the memory device, one or more metadata values characterizing the read voltage level with respect to threshold voltage distributions of the subset of the plurality of memory cells, wherein the one or more metadata values reflect a conductive state of one or more bitlines connected to the subset of the plurality of memory cells.

Abstract: Systems and methods are disclosed including a memory device comprising a memory array and control logic, operatively coupled with the memory array. The control logic can perform operations comprising causing a read operation to be initiated with respect to a set of target cells of the memory array; obtaining, for a respective group of adjacent cells, respective cell state information; performing a set of strobe reads on the set of target cells; and generating, for a target cell of the set of target cells, semi-soft bit data based on the respective cell state information of the respective group of adjacent cells and on data obtained from a first strobe read and a second strobe read of the set of strobe reads performed on the target cell.

Abstract: A processing device in a memory sub-system detects an occurrence of a data integrity check trigger event and, responsive to the occurrence of the data integrity check trigger event, identifies a memory die of a plurality of memory dies. The processing device further associates each segment of the identified memory die with a respective group of a plurality of groups, each group representing one or more of a plurality of error mechanisms, and determines one or more respective adaptive scan frequencies for the identified memory die based on statistics of the segments associated with each respective group.

Abstract: Embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a target read window budget (RWB) increase, wherein the target RWB increase corresponds to a maximum RWB increase associated with using a different PV voltage offset for each respective programming level of a memory cell. Embodiments can also include segmenting the plurality of wordlines into one or more wordline groups, wherein each wordline group comprises one or more wordlines. Embodiments can further include determining, for each wordline group, a target adjustment to a parameter of a memory access operation that is performed with respect to a memory cell associated with a wordline of the wordline group. Embodiments can include determining an aggregate RWB increase for the block in view of the target adjustment to the parameter of the memory access operation.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; responsive to determining that a data integrity metric value satisfies the threshold criterion, performing a first error-handling operation on the data stored on the source set of memory cells; responsive to determining that the first error-handling operation fails to correct the data, performing a second error-handling operation on the data; and responsive to determining that the second error-handling operation corrected the data, causing the memory device to copy the corrected data to a destination set of memory cells of the memory device.

Abstract: Embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a respective value of a sensitivity metric that reflects a sensitivity of a threshold voltage of a memory cell associated with the wordline to a change in a threshold voltage of an adjacent memory cell. Embodiments can also include determining, for the wordline, that the respective value of the sensitivity metric satisfies a threshold criterion. Embodiments can further include responsive to determining that the respective value of the sensitivity metric satisfies the threshold criterion, associating the wordline with a first wordline group, wherein the first wordline group comprises one or more wordlines, and wherein each wordline of the one or more wordlines is associated with a respective value of the sensitivity metric that satisfies the threshold criterion. Embodiments can include performing, on a specified memory cell connected to the wordline associated with the first wordline group, a compensatory operation.

Abstract: A request to access data programmed to a memory sub-system is received. A determination is made of whether memory cells of the memory sub-system that store the programmed data satisfy one or more cell degradation criteria. In response to a determination that the memory cells satisfy the one or more cell degradation criteria, an error correction operation to access the data is performed in accordance with the request.

Abstract: Described are systems and methods for memory read calibration based on memory device-originated metrics characterizing voltage distributions. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first metric characterizing threshold voltage distributions of a subset of the plurality of memory cells; determining a first read voltage adjustment; receiving a second metric characterizing the threshold voltage distributions; determining a second read voltage adjustment; and applying the second read voltage adjustment for reading the subset of the plurality of memory cells.

Abstract: A processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. Responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving data to be stored on the memory device, storing a first copy of the data in a first set of memory cells of the memory device, and storing a second copy of the data in a second set of memory cells of the memory device. The operations can also include reading the first copy of the data and determining whether a threshold voltage of a cell in the first set of memory cells is within an overlapping range of voltage distributions, and reading the second copy of the data and determining whether the threshold voltage of a cell in the second set of memory cells is within an overlapping range of voltage distributions. They can also include using the second copy of the data.

Abstract: A processing device in a memory sub-system monitors a temperature associated with a block of a memory device, the block comprising a plurality of wordlines. The processing device further determines a first amount of time between when memory cells associated with a first wordline of the plurality of wordlines of the block were written and when memory cells associated with a last wordline of the plurality of wordlines of the block were written. That first amount of time is normalized according to the temperature associated with the block. The processing device further determines, based at last in part on the first amount of time and on an associated scaling factor, an estimate of when the block will reach a uniform charge loss state.

Abstract: Embodiments disclosed can include selecting a target read window budget (RWB) increase and identifying a set of aggressor memory cells. They can also include generating a list of programming level states for the set of aggressor memory cells and identifying, in the list, an entry associated with a maximum RWB increase that is greater than or equal to the target RWB increase. They can further include responsive to identifying the entry with the total number of bits associated with a maximum RWB increase that is greater than or equal to the target RWB increase, modifying a parameter of the memory access operation with the adjustment associated with the identified entry.

Abstract: One of a plurality of compaction strategies to be performed on the memory device based on at least one characteristic of a memory device is identified. Each of the plurality of compaction strategies is to program host data from at least one single-level cell (SLC) of the memory device to at least one quad-level cell (QLC) of the memory device. One or more host data from a host system is received. A compaction operation on the one or more host data using the one of the plurality of compaction strategies is performed.

Abstract: Embodiments disclosed can include determining, for each memory cell connected to each wordline, a respective value of a metric that reflects a sensitivity of a threshold voltage associated with the memory cell to a change in a threshold voltage of an adjacent cell and determining, for each wordline, based on the determined sensitivity for each memory cell, a respective aggregate measure of adjacent cell dependence. They can further include comparing the determined aggregate measure of adjacent cell dependence to a threshold dependence value. They can also include identifying a first wordline group having wordlines with high adjacent cell dependence and a second wordline group having wordlines with low adjacent cell dependence and storing a record referencing the wordlines of the second wordline group, the record indicating a corresponding location on the die of the memory device.

Abstract: Embodiments disclosed can include identifying wordline groups where each wordline group is associated with a corresponding default program verify (PV) voltage for each programming level, and determining, for each wordline group, a maximum read window budget (RWB) increase. They can further include defining a target aggregate RWB increase amount based on the maximum RWB increase, and determining, for each wordline group, a minimum number of memory cell programming level groups with corresponding PV voltage offsets sufficient to reach the target aggregate RWB increase amount. The embodiments can also include grouping the programming levels of a specified memory cell into the minimum number of programming level, and applying, based on the specific programming level group containing a target programming level, a corresponding PV voltage offset during a memory cell access operation.

Abstract: Described are systems and methods for memory read calibration based on memory device-originated metadata characterizing voltage distributions. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: receiving one or more metadata values characterizing threshold voltage distributions of a subset of the plurality of memory cells connected to one or more bitlines, wherein the one or more metadata values reflect a conductive state of the one or more bitlines; determining a read voltage adjustment value based on the one or more metadata values; and applying the read voltage adjustment value for reading the subset of the plurality of memory cells.

Abstract: A processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. Responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.

Abstract: Methods, systems, and apparatus for error correction with syndrome computation in a memory device are described. A first syndrome for first encoded data is generated in a memory device. The first syndrome and the first encoded data are transmitted to a controller that is coupled with the memory device. A second syndrome for first and second encoded data is generated. The first encoded data and the second encoded data are interrelated according to an error correction code. The second syndrome is transmitted to the controller without the second encoded data and the controller is to decode the first encoded data based on at least one of the first syndrome, the second syndrome, or a combination thereof.