Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

Abstract: A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines.

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

Abstract: A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines.

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include bonding at least one bond pad of a device side of a first substrate to at least one bond pad of a device side of a second substrate, forming at least one via to connect to at least one of an active feature and an interconnect structure disposed within the first substrate, and forming a reactive material on a surface of at least one of the active features.

Abstract: An apparatus includes a metallization region including a plurality of metal layers on a device layer of a substrate, a via extending through the substrate and the device layer, and a heat spreading and stress engineering region in the substrate and adjacent to the device layer. The via contacts a metal layer in the metallization region.

Abstract: Backside connections for 3D integrated circuits and methods to fabricate thereof are described. A stack of a first wafer over a second wafer that has a substrate of the first wafer on top of the stack, is formed. The substrate of the first wafer is thinned. A first dielectric layer is deposited on the thinned substrate. First vias extending through the substrate to the first wafer are formed in the first dielectric layer. A conductive layer is deposited in the first vias and on the first dielectric layer to form thick conductive lines. Second dielectric layer is formed on the conductive layer. Second vias extending to the conductive lines are formed in the second dielectric layer. Conductive bumps extending into the second vias and offsetting the first vias are formed on the second dielectric layer.