Abstract: In one embodiment, a method for reducing drag includes forming a smooth surface on a first portion of a physical object. The method also includes forming periodic riblets on a second portion of the physical object. The second portion of the physical object is adjacent to the first portion of the physical object. Each riblet of the periodic riblets of the second portion of the physical object is depressed below a plane of the smooth surface of the first portion of the physical object. The method further includes generating a flow over the periodic riblets of the second portion of the physical object and over the smooth surface of the first portion of the physical object. A length of each riblet of the periodic riblets runs parallel to a direction of the flow.

Abstract: This document relates to methods and materials for detecting premalignant and malignant neoplasms. For example, methods and materials for determining whether or not a stool sample from a mammal contains nucleic acid markers or polypeptide markers of a neoplasm are provided.

Abstract: In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.

Abstract: In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.

Abstract: In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.

Abstract: In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.

Abstract: An apparatus, system and method for determining when an LED used in traffic signal device will fail. The traffic signal apparatus comprises a housing, a solid state light disposed therein and having an array of LED generating a light output therefrom, and a circuit adapted to predict failure of the solid state light source based on a plurality of parameters at which the LED array operates. The method comprises the acts of sensing the light output generated by the LED array and sensing the ambient temperature thereby. These sensing acts are then followed by a calculating act wherein a time-average temperature value is calculated based on the intensity of both the light output and the ambient temperature. The calculating act is then followed by another calculating act wherein a time-average duty cycle value of the power source powering the LED array is determined.

Abstract: A phase/frequency detector (18) includes a first memory circuit (50), a second memory circuit (52), a first set circuit (54), a second set circuit (58) and a reset circuit (56). The first memory circuit (50) provides a first output signal (20) in response to the first input signal (12). The second memory circuit (52) provides a second output signal (22) in response to the second input signal (14). The first set circuit (54) initiates the transition of the first memory circuit (50) to the active state, and the second set circuit (58) initiates the transition of the second memory circuit (52) to the active state. The reset circuit (56) initiates the transition of the memory circuits (50, 52) to the inactive state.

Abstract: An integrated circuit (100) contains an analog phase-locked loop circuit having a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector circuit for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG). The voltage controlled oscillator circuit is designed to work with a relatively low regulated voltage, and the regulator circuit is implemented with n-channel devices. The two control voltages respectively effect coarse and fine adjustment of the frequency of the output signal from the phase-locked loop circuit.

Abstract: An integrated circuit (100) includes an analog phase-locked loop circuit (10) and other circuitry (102). The integrated circuit (100) has a plurality of external connection pins (104, 106), which are coupled to the other circuitry. The analog phase-locked loop circuit (10) is free of connections to the external connection pins. The analog phase-locked loop circuit (10) includes a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG) and a regulated supply voltage (VREG).

Abstract: An integrated circuit (100) includes an analog phase-locked loop circuit (10) and other circuitry (102). The analog phase-locked loop circuit includes a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG), one of which also serves as a regulated supply voltage. The regulator circuit includes n-channel devices which are connected in series between a supply voltage and each control voltage output.

Abstract: A lock detector (16) includes a set circuit (64), a reset circuit (120), and a latch circuit (80). The latch circuit (80) provides an output signal (82) in response to the temporal relationship of the first input signal (12) and the second input signal (14). The set circuit (64) initiates the transition of the latch circuit (80) to the locked state, while the reset circuit (120) initiates the transition of the latch circuit (80) to the not-locked state.

Abstract: This invention relates to a method of producing 3-alkanoyloxymethyl-3-cephem-4-carboxylic acids from 3-hydroxymethyl-3-cephem-4-carboxylic acids in an aqueous medium for a practical, large-scale production. Moreover, the invention provides an ideal intermediate for the process.

Abstract: This invention relates to a method of producing 3-alkanoyloxymethyl-3-cephem-4-carboxylic acids from 3-hydroxymethyl-3-cephem-4-carboxylic acids in an aqueous medium for a practical, large-scale production. Moreover, the invention provides an ideal intermediate for the process.