Abstract: A method is presented for distributing cryptographic keys in a hierarchized network including at least one device in charge of a higher group of devices, wherein at least one of the devices of the higher group of devices is also in charge of a lower group of devices. The method includes the steps of: a) storing a set of identifiers particular to the higher group, an identifier particular to the device in charge, an identifier per device in charge of a lower group, each identifier being unique; storing a root cryptographic key; c) providing a root cryptographic key to each device in charge of a lower group using a first non-reversible cryptographic function; d) providing at least one transport cryptographic key to each member of said higher group of devices using a second non-reversible cryptographic function.

Abstract: The invention concerns a random number generator comprising a n-bit LSFR at least one oscillator having at least one delay element introducing a variable delay in the counter feedback loop, and at least one sampling/holding device having at least one input coupled to an output of the oscillator, and at least one output coupled to a input of the LSFR, and a clock input receiving a sampling clock signal at a much lower frequency than the oscillator frequency. Said generator is for example configured to vary the delay introduced by the oscillator delay based on a number q of feedback bits among the n bits of the LSFR output, where q is a an integer such that 1?q?n.

Abstract: A method is presented for distributing cryptographic keys in a hierarchized network including at least one device in charge of a higher group of devices, wherein at least one of the devices of the group of devices is also in charge of a lower group of devices.

Abstract: The invention concerns a random number generator comprising a n-bit LSFR at least one oscillator having at least one delay element introducing a variable delay in the counter feedback loop, and at least one sampling/holding device having at least one input coupled to an output of the oscillator, and at least one output coupled to a input of the LSFR, and a clock input receiving a sampling clock signal at a much lower frequency than the oscillator frequency. Said generator is for example configured to vary the delay introduced by the oscillator delay based on a number q of feedback bits among the n bits of the LSFR output, where q is a an integer such that 1?q?n.

Abstract: The invention concerns a passband Sigma-Delta analog-to-digital converter comprising a first resonator and a second order second resonator, preferably of second order, whereof the respective central frequencies enable a high SNR in a relatively wide frequency band, and a MASH Sigma-Delta analog-to-digital converter incorporating at least two such cascaded converters.

Abstract: The invention concerns a passband Sigma-Delta analog-to-digital converter comprising a first resonator (101) and a second order second resonator (102), preferably of second order, whereof the respective central frequencies are adjustable, so as to enable a high SNR in a relatively wide frequency band, and a MASH Sigma-Delta analog-to-digital converter incorporating at least two such cascaded converters.