Abstract: There is disclosed a high throughput multideposition SACVD reactor that enables the rapid thermal deposition of dielectric materials such as Si3N4, SiO2, and SiON and non-&electric materials such as polysilicon onto a semiconductor substrate in the same chamber according to the desired sequence. Such a reactor has a processing chamber which is well adapted to single semiconductor wafer processing. The processing chamber includes an improved susceptor to support the wafer and a specific gas distribution system adapted to supply the different gases used in the deposition process and for cleaning. The improved susceptor consists of a standard carbon plate coated with a polysilicon film to protect it against said cleaning gases when they are aggressive to carbon. The present invention also encompasses a method of fabricating said improved susceptor.

Abstract: There is disclosed a high throughput multideposition SACVD reactor that enables the rapid thermal deposition of dielectric materials such as Si3N4, SiO2, and SiON and non-dielectric materials such as polysilicon onto a semiconductor substrate in the same chamber according to the desired sequence. Such a reactor has a processing chamber which is well adapted to single semiconductor wafer processing. The processing chamber includes an improved susceptor to support the wafer and a specific gas distribution system adapted to supply the different gases used in the deposition process and for cleaning. The improved susceptor consists of a standard carbon plate coated with a polysilicon film to protect it against said cleaning gases when they are aggressive to carbon. The present invention also encompasses a method of fabricating said improved susceptor.

Abstract: There is disclosed a high throughput multideposition SACVD reactor that enables the rapid thermal deposition of dielectric materials such as Si3N4, SiO2, and SiON and non-dielectric materials such as polysilicon onto a semiconductor substrate in the same chamber according to the desired sequence. Such a reactor has a processing chamber which is well adapted to single semiconductor wafer processing. The processing chamber includes an improved susceptor to support the wafer and a specific gas distribution system adapted to supply the different gases used in the deposition process and for cleaning. The improved susceptor consists of a standard carbon plate coated with a polysilicon film to protect it against said cleaning gases when they are aggressive to carbon. The present invention also encompasses a method of fabricating said improved susceptor.

Abstract: In the fabrication of EDRAM/SDRAM silicon chips with ground rules beyond 0.18 microns, a Si3N4 barrier layer is deposited onto the patterned structure during the borderless polysilicon contact fabrication. It is required that this layer be conformal and has a high hydrogen atom content to prevent junction leakage. These objectives are met with the method of the present invention. In a first embodiment, the Si3N4 layer is deposited in a Rapid Thermal Chemical Vapor Deposition (RTCVD) reactor using a NH3/SiH4 chemistry at a temperature and a pressure in the 600-950° C. and 50-200 Torr ranges respectively. In a second embodiment, it is deposited in a Low Pressure Chemical Vapor Deposition (LPCVD) furnace using a NH3/SiH2Cl2 chemistry (preferred ratio 1:1) at a temperature and a pressure in the 640-700° C. and 0.2-0.8 Torr ranges respectively.

Abstract: The present invention relates generally to an improved ladder boat for supporting semiconductor wafers during thermal treatments which comprises top and bottom plates vertically opposing each other and support rods secured to said plates. Said support rods are provided with dividers for supporting a plurality of wafers one above another in a parallel arrangement. The dividers have a special profile to include a ramp portion so that the wafer is seated at a sharp corner thereof. Therefore, the contact surface between the wafer backside at its periphery and the dividers is segmental or punctual. This contact is preferably performed outside the contact area between the wafer backside and the wafer support zones of the electrostatic chuck of the photolithography tool to be subsequently used in the course of the wafer manufacturing.

Abstract: There is disclosed a method of forming a buried strap (BS) and its quantum conducting barrier (QCB) in a structure wherein a doped polycrystalline silicon region is exposed at the bottom of a recess and separated from a monocrystalline region of a silicon substrate by a region of an insulating material. First, a thin continuous layer of undoped amorphous silicon is deposited by LPCVD to coat said regions. The surface of this layer is nitridized to produce a Si3N4 QCB film. Now, at least one dual layer comprised of an undoped amorphous silicon layer and a dopant monolayer is deposited onto the structure by LPCVD. The recess is filled with undoped amorphous silicon to terminate the buried strap and its QCB. Finally, the structure is heated to activate the dopants in the buried strap to allow an electrical continuity between said polycrystalline and monocrystalline regions through the QCB by a quantum mechanical effect. All these steps are performed in situ in the same LPCVD tool.

Abstract: A multilayered quantum conducting barrier (MQCB) structure formed on two semiconductor regions having a different crystalline nature and a thin layer of an insulating material sandwiched between said semiconductor regions. An undoped amorphous silicon layer continuously coats these two semiconductor regions and insulating layer. The surface of the undoped amorphous silicon layer is nitridized to produce a superficial film of a nitride based material to form the desired quantum conducting barrier (QCB). A stack consisting of at least one dual layer comprised of a bottom undoped amorphous silicon layer and a top dopant monolayer is formed on said undoped amorphous silicon layer. After thermal processing, the MQCB structure operates as a strap allowing an electrical continuity between these semiconductor regions through the QCB by a quantum mechanical effect.

Abstract: Improved reliability structures containing quantum conductive barrier layer structures are obtained by employing quantum conductive layers in combination with thin regions of amorphous or microcrystalline semiconductor material. The quantum conductive structures are especially useful when incorporated into trench capacitors to reduce or eliminate the occurrence of low temperature fails and single cell fails in DRAM circuits.

Abstract: The method of the present invention is directed to the formation of an arsenic silicon glass (ASG) film onto a silicon structure and finds a valuable application in the buried plate region formation process in the manufacture of deep trench cell capacitors in EDO and SDRAM memory chips. The starting structure is state-of-the-art and consists of a silicon substrate coated by a patterned SiO2/Si3N4 pad layer which defines deep trenches formed therein by etching. At the beginning of the conventional buried plate region formation, the interior side walls of deep trenches are coated with an arsenic doped silicon glass (ASG) film resulting from the co-pyrolysis of TEOS and TEASAT in a vertical hot dual wall LPCVD reactor as standard. According to the present invention, a flow of O2 is added which makes this co-pyrolysis of TEOS and TEASAT no longer interactive. As a consequence, the improved process is much better controlled than the conventional one.