Abstract: The invention can provide compounds, analogs of blebbistatin, effective and selective inhibitors of nonmuscle myosin II relative to cardiac myosin II.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Abstract: Programming in a multiprocessor environment includes accepting a program specification that defines a plurality of processing modules and one or more channels for sending data between ports of the modules, mapping each of the processing modules to run on a set of one or more processing engines of a network of interconnected processing engines, and for at least some of the channels, assigning one or more elements of one or more processing engines in the network to the channel for sending data between respective processing modules.

Abstract: Coupling a device to a multicore computing system that includes multiple cores that each include a processor includes sending messages to access memory coupled to at least one of the multiple cores, the memory having an address space, and the messages including a virtual address. An interface is provided for coupling the device to the multicore computing system in a shim that: transmits or receives messages on the communication network among the processors to or from the coupled device, and translates virtual addresses to physical addresses of the address space in response to receiving the messages over the communication network that include a virtual address.

Abstract: Programming in a multiprocessor environment includes accepting a program specification that defines a plurality of processing modules and one or more channels for sending data between ports of the modules, mapping each of the processing modules to run on a set of one or more processing engines of a network of interconnected processing engines, and for at least some of the channels, assigning one or more elements of one or more processing engines in the network to the channel for sending data between respective processing modules.

Abstract: Coupling a device to a multicore computing system that includes multiple cores that each include a processor includes sending messages to access memory coupled to at least one of the multiple cores, the memory having an address space, and the messages including a virtual address. An interface is provided for coupling the device to the multicore computing system in a shim that: transmits or receives messages on the communication network among the processors to or from the coupled device, and translates virtual addresses to physical addresses of the address space in response to receiving the messages over the communication network that include a virtual address.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Abstract: Receiving data at a first device transferred from a second device includes: storing a starting address with respect to a memory address space for a memory of the first device in a storage location within the first device. A request is received at the first device to transfer one or more data values from the second device, the request including a target address with respect to a communication channel address space for a communication channel between the first device and the second device. The second device determines whether the target address corresponds to a reserved address value designated as an indicator of a transfer to a memory address beyond the communication channel address space.

Abstract: The thermal signature of a vehicle is reduced by providing a thermal shield (20) on at least one of the wheels (10) covering at least a greater part of the wheel area, in combination with a further shield (42, 50) around or depending from the wheel arch (19) and which overlaps the wheel-mounted shield (20). The shields (20, 42, 50) may also co-operate to reduce the generation of a dust cloud (45, 46) by the vehicle.

Abstract: An the integrated circuit comprises a plurality of processor cores interconnected by an interconnection network. A method for generating instructions to be executed in the integrated circuit comprises accepting a plurality of programs, at least some of the programs including one or more communication operations to communicate with other programs; mapping each program to one or more of the processor cores; determining correspondence among communication operations in the programs; and mapping communication for corresponding communication operations to resources associated with the interconnection network.