Abstract: A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.

Abstract: A memory device to program a group of memory cells to store multiple bits per memory cell. Each bit per memory cell in the group from a page. After determining a plurality of read voltages of the group of memory cells, the memory device can read the multiple pages of the group using the plurality of read voltages. For each respective page in the multiple pages, the memory device can determine a count of first memory cells in the respective page that have threshold voltages higher than a highest read voltage, among the plurality of read voltages, used to read the respective page. The count of the first memory cells can be compared with a predetermined range of a fraction of memory cells in the respective page to evaluate the plurality of read voltages (e.g., whether any of the read voltages is in a wrong voltage range).

Abstract: A memory sub-system configured to iterative calibrate read voltages, where higher read voltages are calibrated based on the calibration results of lower read voltages. For example, a memory device initially determines first read voltages of a group of memory cells. The memory device calculates a second read voltage optimized to read the group of memory cells according to first signal and noise characteristics measured based on at least one of the first read voltages. A third read voltage is estimated based on an offset of the second read voltage from a corresponding voltage among the first read voltages. Second signal and noise characteristics of the group of memory cells are measured based on the third read voltage. The memory device then calculates a fourth read voltage optimized to read the group of memory cells according to the second signal and noise characteristics.

Abstract: A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.

Abstract: A memory device configured to descramble scrambled composite data. In one approach, the scrambled composite data is provided by an XOR (exclusive OR operation) of more than one data set scrambled with non-linear scramblers. A memory device is configured to receive scramble codes generated by non-linear scramblers and perform an XOR of the scrambled composite data with the scramble codes to remove scrambling from the composite data. In one example, the scrambled data sets are data to be written to a NAND device at more than one bit per cell density (e.g., MLC, TLC, QLC, PLC, etc.). For example, the scrambled data sets may be written to the NAND device in more than one programming pass. In one example, the scrambled composite data is used to read the scrambled data sets that have been written in a first programming pass.

Abstract: A memory sub-system configured to iterative calibrate read voltages, where higher read voltages are calibrated based on the calibration results of lower read voltages. For example, a memory device initially determines first read voltages of a group of memory cells. The memory device calculates a second read voltage optimized to read the group of memory cells according to first signal and noise characteristics measured based on at least one of the first read voltages. A third read voltage is estimated based on an offset of the second read voltage from a corresponding voltage among the first read voltages. Second signal and noise characteristics of the group of memory cells are measured based on the third read voltage. The memory device then calculates a fourth read voltage optimized to read the group of memory cells according to the second signal and noise characteristics.

Abstract: A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.

Abstract: A memory device to perform a calibration of read voltages of a group of memory cells. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine an amount of accumulated storage charge loss in the group of memory cells. Subsequently, the memory device can perform a read voltage calibration based on the determined amount of accumulated storage charge loss and a look up table.

Abstract: A memory sub-system configured to execute a read command of a first type using a combine process to read soft bit data and hard bit data from memory cells. For example, a memory device is to: measure signal and noise characteristics of memory cells for the read command; calculate, based on the characteristics, an optimized voltage and two adjacent voltages that have offsets of a same amount from the optimized voltage; read the memory cells for hard bit data using the optimized voltage and for soft bit data using the two adjacent voltages; and transmit, to the processing device, a response including the hard bit data. The soft bit data can be selectively transmitted based on a classification determined from the characteristics. When a read command of a second type is executed, soft bit data is not read; and/or the signal and noise characteristics are not measured.

Abstract: A memory device to estimate a bit error count of data retrievable from a group of memory cells. For example, the memory device has a group of memory cells programmed to store a predetermined number of bits per memory cells to be read at a plurality of first voltages. The memory device determines a plurality of calibrated read voltages corresponding to the plurality of first voltages respectively, based on first signal and noise characteristics of the group of memory cells. The first signal and noise characteristics are used to compute second signal and noise characteristics of the group of memory cells for the calibrated read voltages. The second signal and noise characteristics are used in an empirical formula to compute an estimate of the bit error count of data retrievable from the group of memory cells using the calibrated read voltages.

Abstract: A memory sub-system configured to improve performance using signal and noise characteristics of memory cells measured during the execution of a command in a memory component. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing the command in the memory component. A processing device separate from the memory component transmits the command to the memory component, and receives and processes the signal and noise characteristics to identify an attribute about the memory component. Subsequently, an operation related to data stored in the memory component can be performed based on the attribute.

Abstract: A memory sub-system configured to adaptively and/or iteratively determine sub-operations of executing a read command to retrieve data from memory cells. For example, after receiving the read command from a processing device of a memory sub-system, a memory device starts an atomic operation of executing the read command in the memory device. The memory device can have one or more groups of memory cells formed on an integrated circuit die and a calibration circuit configured to measure signal and noise characteristics of memory cells in the memory device. During the atomic operation, the calibration circuit generates outputs, based on which a read manager of the memory sub-system identifies sub-operations to be performed in the atomic operation and/or decides to end the atomic operation.

Abstract: A memory sub-system to track charge loss in memory cells and shifts of voltages optimized to read the memory cells. For example, a memory device can measure signal and noise characteristics of a group of memory cells to calculate an optimized read voltage of the group of memory cells. The memory sub-system having the memory device can determine an amount of charge loss in the group of memory cells, using at least the signal and noise characteristics, the optimized read voltage, and/or the bit error rate of data read using the optimized read voltage. The memory sub-system tracks changes in optimized read voltages of memory cells in the memory device based on the amount of charge loss.

Abstract: A memory device to perform a read disturb mitigation operation. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine a margin of read disturb accumulated in the group of memory cells. Subsequently, the memory device can identify the group of memory cells for the read disturb mitigation operation based on the margin of read disturb and a predetermined threshold.

Abstract: A memory device to search for a voltage optimized to read a group of memory cells. In response to a read command, the memory device measures first signal and noise characteristics of the memory cells by reading the memory cells at first test voltages. Based on the first signal and noise characteristics, the memory device may determine that the optimized read voltage is outside of a range of the first test voltages. In response, the memory device determines, based on the first signal and noise characteristics, an estimate of the optimized read voltage, and measures second signal and noise characteristics by reading at second test voltages configured around the estimate. The optimized read voltage can be computed based at least in part on the second signal and noise characteristics. The memory device retrieves data from the memory cells using the optimized read voltage.

Abstract: A memory device to determine a voltage window to read soft bit data. For example, in response to a read command, the memory device can read a group of memory cells at a plurality of test voltages to determine signal and noise characteristics, which can be used to determine an optimized read voltage for reading hard bit data and a voltage window between a first voltage and a second voltage for reading soft bit data. The soft bit data identifies exclusive or (XOR) of results read from the group of memory cells at the first voltage and at the second voltage respective. The memory device can provide a response to the read command based on the hard bit data and the soft bit data.

Abstract: A memory device to perform a calibration of read voltages of a group of memory cells. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine an amount of accumulated storage charge loss in the group of memory cells. Subsequently, the memory device can perform a read voltage calibration based on the determined amount of accumulated storage charge loss and a look up table.

Abstract: A memory device configured to descramble scrambled composite data. In one approach, the scrambled composite data is provided by an XOR (exclusive OR operation) of more than one data set scrambled with non-linear scramblers. A memory device is configured to receive scramble codes generated by non-linear scramblers and perform an XOR of the scrambled composite data with the scramble codes to remove scrambling from the composite data. In one example, the scrambled data sets are data to be written to a NAND device at more than one bit per cell density (e.g., MLC, TLC, QLC, PLC, etc.). For example, the scrambled data sets may be written to the NAND device in more than one programming pass. In one example, the scrambled composite data is used to read the scrambled data sets that have been written in a first programming pass.

Abstract: A memory device to manage the assignment of offset voltages for read operations, and to adjust read voltages using the offset voltages. The offset voltages are dynamically adjusted by a controller during operation of the memory device in response to read errors. In one approach, a first bin of offset voltages is assigned to a first region of a storage media. The first offset voltages are used to adjust read voltages for reading a page of first memory cells in the first region. The controller determines that at least one error has occurred in reading the page. In response to determining the error, the controller determines second offset voltages that can be used to read the first memory cell without causing a read error. Based on the second offset voltages, the controller identifies third offset voltages for assigning to the first region. The third offset voltages are used for adjusting read voltages for subsequent reads of pages in the first region.

Abstract: A memory device to perform a read disturb scan of unprogrammed memory cells. In one approach, a test read is performed on unprogrammed memory cells in a first memory block of a storage media (e.g., NAND flash) to provide a test result. Based on the test result, a portion of the unprogrammed cells for which a threshold voltage is above a predetermined voltage is determined. A determination is made whether the portion of the unprogrammed memory cells exceeds a predetermined limit. In response to determining that the portion exceeds the predetermined limit, data is moved from the first memory block to a second memory block of the storage media.