Patents by Inventor Patrick S. Spinney
Patrick S. Spinney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10699973Abstract: A test structure for semiconductor chips of a wafer, and the method of forming the same is included. The test structure may include a first portion disposed within a corner area of a first chip on the wafer, and at least another portion disposed within another corner of another chip on the wafer, wherein before dicing of the chips, the portions form the test structure. The test structure may include an electronic test structure or an optical test structure. The electronic test structure may include probe pads, each probe pad positioned across two or more corner areas of two or more chips. The corner areas including the test structures disposed therein may be removed from the chips during a dicing of the chips.Type: GrantFiled: November 6, 2017Date of Patent: June 30, 2020Assignee: GLOBALFOUNDERS INC.Inventors: Anthony K. Stamper, Patrick S. Spinney, Jeffrey C. Stamm
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Publication number: 20190139841Abstract: A test structure for semiconductor chips of a wafer, and the method of forming the same is included. The test structure may include a first portion disposed within a corner area of a first chip on the wafer, and at least another portion disposed within another corner of another chip on the wafer, wherein before dicing of the chips, the portions form the test structure. The test structure may include an electronic test structure or an optical test structure. The electronic test structure may include probe pads, each probe pad positioned across two or more corner areas of two or more chips. The corner areas including the test structures disposed therein may be removed from the chips during a dicing of the chips.Type: ApplicationFiled: November 6, 2017Publication date: May 9, 2019Inventors: Anthony K. Stamper, Patrick S. Spinney, Jeffrey C. Stamm
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Patent number: 10141274Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.Type: GrantFiled: October 31, 2017Date of Patent: November 27, 2018Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
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Patent number: 10056306Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.Type: GrantFiled: February 4, 2016Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Edward C. Cooney, III, Gary L. Milo, Thomas W. Weeks, Patrick S. Spinney, John C. Hall, Brian P. Conchieri, Brett T. Cucci, Thomas C. Lee
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Publication number: 20180053734Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.Type: ApplicationFiled: October 31, 2017Publication date: February 22, 2018Inventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
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Patent number: 9893023Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.Type: GrantFiled: May 26, 2017Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
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Publication number: 20170263574Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.Type: ApplicationFiled: May 26, 2017Publication date: September 14, 2017Inventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
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Publication number: 20170229358Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.Type: ApplicationFiled: February 4, 2016Publication date: August 10, 2017Inventors: Edward C. Cooney, III, Gary L. Milo, Thomas W. Weeks, Patrick S. Spinney, John C. Hall, Brian P. Conchieri, Brett T. Cucci, Thomas C. Lee
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Patent number: 9711464Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.Type: GrantFiled: September 23, 2015Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
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Publication number: 20170084552Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.Type: ApplicationFiled: September 23, 2015Publication date: March 23, 2017Inventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
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Patent number: 9553061Abstract: The present disclosure relates to semiconductor structures and, more particularly, to wire bond pad structures and methods of manufacture. The structure includes: bond pads in an active region of a chip; test pad structures in a kerf region of the chip; and hardmask material in the kerf region between the test pad structures and the bond pads. The surfaces of the test pad structures and the bond pads are devoid of the hardmask material.Type: GrantFiled: November 19, 2015Date of Patent: January 24, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Donald R. Letourneau, Patrick S. Spinney, Leah J. Bagley, John M. Sutton